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drm/msm/a5xx: Disable UCHE global filter

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Port over the command from downstream to prevent undefined
behaviour.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Konrad Dybcio 2021-01-13 19:33:39 +01:00 committed by Rob Clark
parent cce212d844
commit 3f2bc3856b
2 changed files with 5 additions and 0 deletions
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2
drivers/gpu/drm/msm/adreno/a5xx.xml.h
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@ -2367,6 +2367,8 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
#define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80 #define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80
#define REG_A5XX_UCHE_MODE_CNTL 0x00000e81
#define REG_A5XX_UCHE_SVM_CNTL 0x00000e82 #define REG_A5XX_UCHE_SVM_CNTL 0x00000e82
#define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87 #define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87

3
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
View File

@ -754,6 +754,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
adreno_is_a512(adreno_gpu)) adreno_is_a512(adreno_gpu))
gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9)); gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9));
/* Disable UCHE global filter as SP can invalidate/flush independently */
gpu_write(gpu, REG_A5XX_UCHE_MODE_CNTL, BIT(29));
/* Enable USE_RETENTION_FLOPS */ /* Enable USE_RETENTION_FLOPS */
gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000); gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000);