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ARM: dts: uniphier: add reset-names to NAND controller node

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The Denali NAND controller IP has separate reset control for the
controller core and registers.

Add the reset-names, and one more phandle accordingly. This is the
approved DT-binding.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada 2020-01-16 21:50:44 +09:00
parent 38dbf2de46
commit 37f3e0096f
5 changed files with 10 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/boot/dts/uniphier-ld4.dtsi
View File

@ -410,7 +410,8 @@
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
resets = <&sys_rst 2>;
reset-names = "nand", "reg";
resets = <&sys_rst 2>, <&sys_rst 2>;
};
};
};

3
arch/arm/boot/dts/uniphier-pro4.dtsi
View File

@ -600,7 +600,8 @@
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
resets = <&sys_rst 2>;
reset-names = "nand", "reg";
resets = <&sys_rst 2>, <&sys_rst 2>;
};
};
};

3
arch/arm/boot/dts/uniphier-pro5.dtsi
View File

@ -465,7 +465,8 @@
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
resets = <&sys_rst 2>;
reset-names = "nand", "reg";
resets = <&sys_rst 2>, <&sys_rst 2>;
};
emmc: sdhc@68400000 {

3
arch/arm/boot/dts/uniphier-pxs2.dtsi
View File

@ -773,7 +773,8 @@
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
resets = <&sys_rst 2>;
reset-names = "nand", "reg";
resets = <&sys_rst 2>, <&sys_rst 2>;
};
};
};

3
arch/arm/boot/dts/uniphier-sld8.dtsi
View File

@ -414,7 +414,8 @@
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
resets = <&sys_rst 2>;
reset-names = "nand", "reg";
resets = <&sys_rst 2>, <&sys_rst 2>;
};
};
};