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drm/amd/display: Increase timeout threshold for DMCUB reset
[Why] If we're backdoor loading the DMCUB performs more work than just the PHY reset so we can end up resetting before the cleanup has fully finished. [How] Increase timeout, add udelay between spins to guarantee a minimum. Reviewed-by: Roy Chan <roy.chan@amd.com> Reviewed-by: Eric Yang <Eric.Yang2@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -83,7 +83,7 @@ static inline void dmub_dcn31_translate_addr(const union dmub_addr *addr_in,
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void dmub_dcn31_reset(struct dmub_srv *dmub)
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void dmub_dcn31_reset(struct dmub_srv *dmub)
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{
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{
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union dmub_gpint_data_register cmd;
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union dmub_gpint_data_register cmd;
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const uint32_t timeout = 30;
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const uint32_t timeout = 100;
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uint32_t in_reset, scratch, i;
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uint32_t in_reset, scratch, i;
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REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
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REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
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@ -98,21 +98,21 @@ void dmub_dcn31_reset(struct dmub_srv *dmub)
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/**
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/**
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* Timeout covers both the ACK and the wait
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* Timeout covers both the ACK and the wait
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* for remaining work to finish.
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* for remaining work to finish.
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*
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* This is mostly bound by the PHY disable sequence.
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* Each register check will be greater than 1us, so
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* don't bother using udelay.
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*/
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*/
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for (i = 0; i < timeout; ++i) {
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for (i = 0; i < timeout; ++i) {
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if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
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if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
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break;
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break;
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udelay(1);
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}
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}
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for (i = 0; i < timeout; ++i) {
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for (i = 0; i < timeout; ++i) {
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scratch = dmub->hw_funcs.get_gpint_response(dmub);
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scratch = dmub->hw_funcs.get_gpint_response(dmub);
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if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
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if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
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break;
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break;
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udelay(1);
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}
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}
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/* Force reset in case we timed out, DMCUB is likely hung. */
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/* Force reset in case we timed out, DMCUB is likely hung. */
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