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drm/amd/pm: update the data type for retrieving enabled ppfeatures

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Use uint64_t instead of an array of uint32_t. This can avoid
some non-necessary intermediate uint32_t -> uint64_t conversions.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan 2021-12-08 13:01:43 +08:00 committed by Alex Deucher
parent 5af779adc3
commit 2d282665d2
14 changed files with 32 additions and 64 deletions
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2
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
View File

@ -2341,7 +2341,7 @@ static int smu_read_sensor(void *handle,
*size = 4;
break;
case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data);
*size = 8;
break;
case AMDGPU_PP_SENSOR_UVD_POWER:

5
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
View File

@ -989,10 +989,9 @@ struct pptable_funcs {
/**
* @get_enabled_mask: Get a mask of features that are currently enabled
* on the SMU.
* &feature_mask: Array representing enabled feature mask.
* &num: Elements in &feature_mask.
* &feature_mask: Enabled feature mask.
*/
int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask);
/**
* @feature_is_enabled: Test if a feature is enabled.

5
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
View File

@ -2021,15 +2021,12 @@ static void arcturus_dump_pptable(struct smu_context *smu)
static bool arcturus_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
uint32_t feature_mask[2];
uint64_t feature_enabled;
ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
return !!(feature_enabled & SMC_DPM_FEATURE);
}

6
drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
View File

@ -350,20 +350,16 @@ static bool cyan_skillfish_is_dpm_running(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
int ret = 0;
uint32_t feature_mask[2];
uint64_t feature_enabled;
/* we need to re-init after suspend so return false */
if (adev->in_suspend)
return false;
ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
feature_enabled = (uint64_t)feature_mask[0] |
((uint64_t)feature_mask[1] << 32);
/*
* cyan_skillfish specific, query default sclk inseted of hard code.
*/

5
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
View File

@ -1639,15 +1639,12 @@ static int navi10_display_config_changed(struct smu_context *smu)
static bool navi10_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
uint32_t feature_mask[2];
uint64_t feature_enabled;
ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
return !!(feature_enabled & SMC_DPM_FEATURE);
}

5
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
View File

@ -1297,15 +1297,12 @@ static int sienna_cichlid_display_config_changed(struct smu_context *smu)
static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
uint32_t feature_mask[2];
uint64_t feature_enabled;
ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
return !!(feature_enabled & SMC_DPM_FEATURE);
}

4
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
View File

@ -799,7 +799,7 @@ int smu_v11_0_system_features_control(struct smu_context *smu,
bool en)
{
struct smu_feature *feature = &smu->smu_feature;
uint32_t feature_mask[2];
uint64_t feature_mask;
int ret = 0;
ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
@ -811,7 +811,7 @@ int smu_v11_0_system_features_control(struct smu_context *smu,
bitmap_zero(feature->supported, feature->feature_num);
if (en) {
ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
ret = smu_cmn_get_enabled_mask(smu, &feature_mask);
if (ret)
return ret;

10
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
View File

@ -500,21 +500,17 @@ static bool vangogh_is_dpm_running(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
int ret = 0;
uint32_t feature_mask[2];
uint64_t feature_enabled;
/* we need to re-init after suspend so return false */
if (adev->in_suspend)
return false;
ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
((uint64_t)feature_mask[1] << 32));
return !!(feature_enabled & SMC_DPM_FEATURE);
}
@ -1952,7 +1948,7 @@ static int vangogh_system_features_control(struct smu_context *smu, bool en)
{
struct amdgpu_device *adev = smu->adev;
struct smu_feature *feature = &smu->smu_feature;
uint32_t feature_mask[2];
uint64_t feature_mask;
int ret = 0;
if (adev->pm.fw_version >= 0x43f1700 && !en)
@ -1965,7 +1961,7 @@ static int vangogh_system_features_control(struct smu_context *smu, bool en)
if (!en)
return ret;
ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
ret = smu_cmn_get_enabled_mask(smu, &feature_mask);
if (ret)
return ret;

7
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
View File

@ -1450,14 +1450,11 @@ static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_
static bool aldebaran_is_dpm_running(struct smu_context *smu)
{
int ret;
uint32_t feature_mask[2];
unsigned long feature_enabled;
uint64_t feature_enabled;
ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
((uint64_t)feature_mask[1] << 32));
return !!(feature_enabled & SMC_DPM_FEATURE);
}

4
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
View File

@ -765,7 +765,7 @@ int smu_v13_0_system_features_control(struct smu_context *smu,
bool en)
{
struct smu_feature *feature = &smu->smu_feature;
uint32_t feature_mask[2];
uint64_t feature_mask;
int ret = 0;
ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
@ -777,7 +777,7 @@ int smu_v13_0_system_features_control(struct smu_context *smu,
bitmap_zero(feature->supported, feature->feature_num);
if (en) {
ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
ret = smu_cmn_get_enabled_mask(smu, &feature_mask);
if (ret)
return ret;

9
drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
View File

@ -197,7 +197,7 @@ static int yellow_carp_system_features_control(struct smu_context *smu, bool en)
{
struct smu_feature *feature = &smu->smu_feature;
struct amdgpu_device *adev = smu->adev;
uint32_t feature_mask[2];
uint64_t feature_mask;
int ret = 0;
if (!en && !adev->in_s0ix)
@ -209,7 +209,7 @@ static int yellow_carp_system_features_control(struct smu_context *smu, bool en)
if (!en)
return ret;
ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
ret = smu_cmn_get_enabled_mask(smu, &feature_mask);
if (ret)
return ret;
@ -255,16 +255,13 @@ static int yellow_carp_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
static bool yellow_carp_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
uint32_t feature_mask[2];
uint64_t feature_enabled;
ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
return !!(feature_enabled & SMC_DPM_FEATURE);
}

29
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
View File

@ -542,8 +542,7 @@ bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
}
int smu_cmn_get_enabled_mask(struct smu_context *smu,
uint32_t *feature_mask,
uint32_t num)
uint64_t *feature_mask)
{
struct smu_feature *feature = &smu->smu_feature;
struct amdgpu_device *adev = smu->adev;
@ -551,7 +550,7 @@ int smu_cmn_get_enabled_mask(struct smu_context *smu,
uint32_t *feature_mask_low;
int ret = 0;
if (!feature_mask || num < 2)
if (!feature_mask)
return -EINVAL;
if (!bitmap_empty(feature->enabled, feature->feature_num)) {
@ -561,8 +560,8 @@ int smu_cmn_get_enabled_mask(struct smu_context *smu,
return 0;
}
feature_mask_low = &feature_mask[0];
feature_mask_high = &feature_mask[1];
feature_mask_low = &((uint32_t *)feature_mask)[0];
feature_mask_high = &((uint32_t *)feature_mask)[1];
switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(11, 0, 8):
@ -695,7 +694,7 @@ static const char *smu_get_feature_name(struct smu_context *smu,
size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
char *buf)
{
uint32_t feature_mask[2] = { 0 };
uint64_t feature_mask;
int feature_index = 0;
uint32_t count = 0;
int8_t sort_feature[SMU_FEATURE_COUNT];
@ -703,13 +702,12 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
int ret = 0, i;
ret = smu_cmn_get_enabled_mask(smu,
feature_mask,
2);
&feature_mask);
if (ret)
return 0;
size = sysfs_emit_at(buf, size, "features high: 0x%08x low: 0x%08x\n",
feature_mask[1], feature_mask[0]);
upper_32_bits(feature_mask), lower_32_bits(feature_mask));
memset(sort_feature, -1, sizeof(sort_feature));
@ -745,22 +743,17 @@ int smu_cmn_set_pp_feature_mask(struct smu_context *smu,
uint64_t new_mask)
{
int ret = 0;
uint32_t feature_mask[2] = { 0 };
uint64_t feature_mask;
uint64_t feature_2_enabled = 0;
uint64_t feature_2_disabled = 0;
uint64_t feature_enables = 0;
ret = smu_cmn_get_enabled_mask(smu,
feature_mask,
2);
&feature_mask);
if (ret)
return ret;
feature_enables = ((uint64_t)feature_mask[1] << 32 |
(uint64_t)feature_mask[0]);
feature_2_enabled = ~feature_enables & new_mask;
feature_2_disabled = feature_enables & ~new_mask;
feature_2_enabled = ~feature_mask & new_mask;
feature_2_disabled = feature_mask & ~new_mask;
if (feature_2_enabled) {
ret = smu_cmn_feature_update_enable_state(smu,

3
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
View File

@ -58,8 +58,7 @@ bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
enum smu_clk_type clk_type);
int smu_cmn_get_enabled_mask(struct smu_context *smu,
uint32_t *feature_mask,
uint32_t num);
uint64_t *feature_mask);
uint64_t smu_cmn_get_indep_throttler_status(
const unsigned long dep_status,

2
drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
View File

@ -55,7 +55,7 @@
#define smu_send_smc_msg(smu, msg, read_arg) smu_ppt_funcs(send_smc_msg, 0, smu, msg, read_arg)
#define smu_init_display_count(smu, count) smu_ppt_funcs(init_display_count, 0, smu, count)
#define smu_feature_set_allowed_mask(smu) smu_ppt_funcs(set_allowed_mask, 0, smu)
#define smu_feature_get_enabled_mask(smu, mask, num) smu_ppt_funcs(get_enabled_mask, 0, smu, mask, num)
#define smu_feature_get_enabled_mask(smu, mask) smu_ppt_funcs(get_enabled_mask, 0, smu, mask)
#define smu_feature_is_enabled(smu, mask) smu_ppt_funcs(feature_is_enabled, 0, smu, mask)
#define smu_disable_all_features_with_exception(smu, no_hw_disablement, mask) smu_ppt_funcs(disable_all_features_with_exception, 0, smu, no_hw_disablement, mask)
#define smu_is_dpm_running(smu) smu_ppt_funcs(is_dpm_running, 0 , smu)