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dt-bindings: perf: Convert Arm DSU to schema

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Convert the DSU binding to schema, as one does.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/9fde2e11b0d11285c26d0e9d261034a1628c7901.1639490264.git.robin.murphy@arm.com
Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Robin Murphy 2021-12-14 14:16:16 +00:00 committed by Rob Herring
parent 570df0a519
commit 2d0b208b3b
2 changed files with 41 additions and 27 deletions
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27
Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
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* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores
with a shared L3 memory system, control logic and external interfaces to
form a multicore cluster. The PMU enables to gather various statistics on
the operations of the DSU. The PMU provides independent 32bit counters that
can count any of the supported events, along with a 64bit cycle counter.
The PMU is accessed via CPU system registers and has no MMIO component.
** DSU PMU required properties:
- compatible : should be one of :
"arm,dsu-pmu"
- interrupts : Exactly 1 SPI must be listed.
- cpus : List of phandles for the CPUs connected to this DSU instance.
** Example:
dsu-pmu-0 {
compatible = "arm,dsu-pmu";
interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;
cpus = <&cpu_0>, <&cpu_1>;
};

41
Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2021 Arm Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
maintainers:
- Suzuki K Poulose <suzuki.poulose@arm.com>
- Robin Murphy <robin.murphy@arm.com>
description:
ARM DynamIQ Shared Unit (DSU) integrates one or more CPU cores with a shared
L3 memory system, control logic and external interfaces to form a multicore
cluster. The PMU enables gathering various statistics on the operation of the
DSU. The PMU provides independent 32-bit counters that can count any of the
supported events, along with a 64-bit cycle counter. The PMU is accessed via
CPU system registers and has no MMIO component.
properties:
compatible:
const: arm,dsu-pmu
interrupts:
items:
- description: nCLUSTERPMUIRQ interrupt
cpus:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 8
description: List of phandles for the CPUs connected to this DSU instance.
required:
- compatible
- interrupts
- cpus
additionalProperties: false