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wifi: rtw89: debug: txpwr table supports Wi-Fi 7 chips
We add TX power table format for Wi-Fi 7 chips. Since Wi-Fi 7 tables are larger, in order to reuse some chunks, we extend code to process nested entries. Now, dbgfs txpwr_table can work with Wi-Fi 7 chips. An output example of dbgfs txpwr_table on Wi-Fi 7 chips is shown below. ... [TX power byrate] << BW20 >> CCK - 1M 2M 5.5M 11M | 20, 20, 20, 20, dBm LEGACY - 6M 9M 12M 18M | 18, 18, 18, 18, dBm LEGACY - 24M 36M 48M 54M | 18, 18, 17, 16, dBm EHT - MCS14 MCS15 | 0, 0, dBm DLRU_EHT - MCS14 MCS15 | 0, 18, dBm MCS_1SS - MCS0 MCS1 MCS2 MCS3 | 18, 18, 18, 18, dBm MCS_1SS - MCS4 MCS5 MCS6 MCS7 | 18, 17, 16, 15, dBm MCS_1SS - MCS8 MCS9 MCS10 MCS11 | 14, 13, 12, 11, dBm MCS_1SS - MCS12 MCS13 | 10, 9, dBm HEDCM_1SS - MCS0 MCS1 MCS3 MCS4 | 18, 18, 18, 18, dBm DLRU_MCS_1SS - MCS0 MCS1 MCS2 MCS3 | 18, 18, 18, 18, dBm DLRU_MCS_1SS - MCS4 MCS5 MCS6 MCS7 | 18, 17, 16, 15, dBm DLRU_MCS_1SS - MCS8 MCS9 MCS10 MCS11 | 14, 13, 12, 11, dBm DLRU_MCS_1SS - MCS12 MCS13 | 10, 9, dBm DLRU_HEDCM_1SS - MCS0 MCS1 MCS3 MCS4 | 18, 18, 18, 18, dBm MCS_2SS - MCS0 MCS1 MCS2 MCS3 | 18, 18, 18, 18, dBm ... [TX power limit] << 1TX >> CCK_20M - NON_BF BF | 0, 0, dBm CCK_40M - NON_BF BF | 0, 0, dBm OFDM - NON_BF BF | 18, 0, dBm MCS_20M_0 - NON_BF BF | 18, 0, dBm MCS_20M_1 - NON_BF BF | 0, 0, dBm ... Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20231003015446.14658-8-pkshih@realtek.com
This commit is contained in:
Zong-Zhe Yang
Kalle Valo
parent
f680fc5695
commit
036042e157
@ -367,7 +367,11 @@ static int rtw89_debug_priv_rf_reg_dump_get(struct seq_file *m, void *v)
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}
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struct txpwr_ent {
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const char *txt;
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bool nested;
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union {
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const char *txt;
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const struct txpwr_ent *ptr;
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};
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u8 len;
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};
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@ -379,6 +383,12 @@ struct txpwr_map {
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u32 addr_to_1ss;
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};
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#define __GEN_TXPWR_ENT_NESTED(_e) \
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{ .nested = true, .ptr = __txpwr_ent_##_e, \
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.len = ARRAY_SIZE(__txpwr_ent_##_e) }
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#define __GEN_TXPWR_ENT0(_t) { .len = 0, .txt = _t }
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#define __GEN_TXPWR_ENT2(_t, _e0, _e1) \
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{ .len = 2, .txt = _t "\t- " _e0 " " _e1 }
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@ -501,14 +511,196 @@ static const struct txpwr_map __txpwr_map_lmt_ru_ax = {
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.addr_to_1ss = R_AX_PWR_RU_LMT_1SS_MAX,
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};
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static u8 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent,
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const s8 *buf, const u8 cur)
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static const struct txpwr_ent __txpwr_ent_byr_mcs_be[] = {
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__GEN_TXPWR_ENT4("MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
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__GEN_TXPWR_ENT4("MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
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__GEN_TXPWR_ENT4("MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
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__GEN_TXPWR_ENT2("MCS_1SS ", "MCS12 ", "MCS13 \t"),
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__GEN_TXPWR_ENT4("HEDCM_1SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
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__GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
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__GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
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__GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
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__GEN_TXPWR_ENT2("DLRU_MCS_1SS ", "MCS12 ", "MCS13 \t"),
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__GEN_TXPWR_ENT4("DLRU_HEDCM_1SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
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__GEN_TXPWR_ENT4("MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
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__GEN_TXPWR_ENT4("MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
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__GEN_TXPWR_ENT4("MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
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__GEN_TXPWR_ENT2("MCS_2SS ", "MCS12 ", "MCS13 \t"),
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__GEN_TXPWR_ENT4("HEDCM_2SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
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__GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
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__GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
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__GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
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__GEN_TXPWR_ENT2("DLRU_MCS_2SS ", "MCS12 ", "MCS13 \t"),
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__GEN_TXPWR_ENT4("DLRU_HEDCM_2SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
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};
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static const struct txpwr_ent __txpwr_ent_byr_be[] = {
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__GEN_TXPWR_ENT0("BW20"),
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__GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "),
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__GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "),
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__GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "),
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__GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"),
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__GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"),
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__GEN_TXPWR_ENT_NESTED(byr_mcs_be),
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__GEN_TXPWR_ENT0("BW40"),
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__GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "),
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__GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "),
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__GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "),
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__GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"),
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__GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"),
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__GEN_TXPWR_ENT_NESTED(byr_mcs_be),
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/* there is no CCK section after BW80 */
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__GEN_TXPWR_ENT0("BW80"),
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__GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "),
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__GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "),
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__GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"),
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__GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"),
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__GEN_TXPWR_ENT_NESTED(byr_mcs_be),
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__GEN_TXPWR_ENT0("BW160"),
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__GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "),
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__GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "),
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__GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"),
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__GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"),
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__GEN_TXPWR_ENT_NESTED(byr_mcs_be),
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__GEN_TXPWR_ENT0("BW320"),
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__GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "),
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__GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "),
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__GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"),
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__GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"),
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__GEN_TXPWR_ENT_NESTED(byr_mcs_be),
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};
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static const struct txpwr_map __txpwr_map_byr_be = {
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.ent = __txpwr_ent_byr_be,
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.size = ARRAY_SIZE(__txpwr_ent_byr_be),
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.addr_from = R_BE_PWR_BY_RATE,
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.addr_to = R_BE_PWR_BY_RATE_MAX,
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.addr_to_1ss = 0, /* not support */
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};
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static const struct txpwr_ent __txpwr_ent_lmt_mcs_be[] = {
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__GEN_TXPWR_ENT2("MCS_20M_0 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_20M_1 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_20M_2 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_20M_3 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_20M_4 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_20M_5 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_20M_6 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_20M_7 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_20M_8 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_20M_9 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_20M_10 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_20M_11 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_20M_12 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_20M_13 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_20M_14 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_20M_15 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_40M_0 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_40M_1 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_40M_2 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_40M_3 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_40M_4 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_40M_5 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_40M_6 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_40M_7 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_80M_0 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_80M_1 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_80M_2 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_80M_3 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_160M_0 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_160M_1 ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_320M ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_40M_0p5", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_40M_2p5", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_40M_4p5", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("MCS_40M_6p5", "NON_BF", "BF"),
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};
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static const struct txpwr_ent __txpwr_ent_lmt_be[] = {
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__GEN_TXPWR_ENT0("1TX"),
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__GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT_NESTED(lmt_mcs_be),
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__GEN_TXPWR_ENT0("2TX"),
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__GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"),
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__GEN_TXPWR_ENT_NESTED(lmt_mcs_be),
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};
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static const struct txpwr_map __txpwr_map_lmt_be = {
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.ent = __txpwr_ent_lmt_be,
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.size = ARRAY_SIZE(__txpwr_ent_lmt_be),
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.addr_from = R_BE_PWR_LMT,
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.addr_to = R_BE_PWR_LMT_MAX,
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.addr_to_1ss = 0, /* not support */
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};
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static const struct txpwr_ent __txpwr_ent_lmt_ru_indexes_be[] = {
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__GEN_TXPWR_ENT8("RU26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ",
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"IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "),
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__GEN_TXPWR_ENT8("RU26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11",
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"IDX_12", "IDX_13", "IDX_14", "IDX_15"),
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__GEN_TXPWR_ENT8("RU52 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ",
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"IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "),
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__GEN_TXPWR_ENT8("RU52 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11",
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"IDX_12", "IDX_13", "IDX_14", "IDX_15"),
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__GEN_TXPWR_ENT8("RU106 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ",
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"IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "),
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__GEN_TXPWR_ENT8("RU106 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11",
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"IDX_12", "IDX_13", "IDX_14", "IDX_15"),
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__GEN_TXPWR_ENT8("RU52_26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ",
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"IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "),
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__GEN_TXPWR_ENT8("RU52_26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11",
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"IDX_12", "IDX_13", "IDX_14", "IDX_15"),
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__GEN_TXPWR_ENT8("RU106_26", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ",
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"IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "),
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__GEN_TXPWR_ENT8("RU106_26", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11",
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"IDX_12", "IDX_13", "IDX_14", "IDX_15"),
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};
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static const struct txpwr_ent __txpwr_ent_lmt_ru_be[] = {
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__GEN_TXPWR_ENT0("1TX"),
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__GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be),
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__GEN_TXPWR_ENT0("2TX"),
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__GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be),
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};
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static const struct txpwr_map __txpwr_map_lmt_ru_be = {
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.ent = __txpwr_ent_lmt_ru_be,
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.size = ARRAY_SIZE(__txpwr_ent_lmt_ru_be),
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.addr_from = R_BE_PWR_RU_LMT,
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.addr_to = R_BE_PWR_RU_LMT_MAX,
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.addr_to_1ss = 0, /* not support */
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};
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static unsigned int
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__print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent,
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const s8 *buf, const unsigned int cur)
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{
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unsigned int cnt, i;
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char *fmt;
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if (ent->nested) {
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for (cnt = 0, i = 0; i < ent->len; i++)
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cnt += __print_txpwr_ent(m, ent->ptr + i, buf,
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cur + cnt);
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return cnt;
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}
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switch (ent->len) {
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case 0:
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seq_printf(m, "\t<< %s >>\n", ent->txt);
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return 0;
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case 2:
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fmt = "%s\t| %3d, %3d,\tdBm\n";
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fmt = "%s\t| %3d, %3d,\t\tdBm\n";
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seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1]);
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return 2;
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case 4:
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@ -532,10 +724,10 @@ static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev,
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{
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u8 fct = rtwdev->chip->txpwr_factor_mac;
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u8 path_num = rtwdev->chip->rf_path_num;
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unsigned int cur, i;
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u32 max_valid_addr;
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u32 val, addr;
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s8 *buf, tmp;
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u8 cur, i;
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int ret;
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buf = vzalloc(map->addr_to - map->addr_from + 4);
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@ -547,6 +739,9 @@ static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev,
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else
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max_valid_addr = map->addr_to;
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if (max_valid_addr == 0)
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return -EOPNOTSUPP;
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for (addr = map->addr_from; addr <= max_valid_addr; addr += 4) {
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ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val);
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if (ret)
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@ -612,8 +807,15 @@ static const struct dbgfs_txpwr_table dbgfs_txpwr_table_ax = {
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.lmt_ru = &__txpwr_map_lmt_ru_ax,
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};
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static const struct dbgfs_txpwr_table dbgfs_txpwr_table_be = {
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.byr = &__txpwr_map_byr_be,
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.lmt = &__txpwr_map_lmt_be,
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.lmt_ru = &__txpwr_map_lmt_ru_be,
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};
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static const struct dbgfs_txpwr_table *dbgfs_txpwr_tables[RTW89_CHIP_GEN_NUM] = {
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[RTW89_CHIP_AX] = &dbgfs_txpwr_table_ax,
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[RTW89_CHIP_BE] = &dbgfs_txpwr_table_be,
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};
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static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v)
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@ -3943,8 +3943,11 @@
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#define R_BE_PWR_RATE_OFST_CTRL 0x11A30
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#define R_BE_PWR_BY_RATE 0x11E00
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#define R_BE_PWR_BY_RATE_MAX 0x11FA8
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#define R_BE_PWR_LMT 0x11FAC
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#define R_BE_PWR_LMT_MAX 0x12040
|
||||
#define R_BE_PWR_RU_LMT 0x12048
|
||||
#define R_BE_PWR_RU_LMT_MAX 0x120E4
|
||||
|
||||
#define CMAC1_START_ADDR_BE 0x14000
|
||||
#define CMAC1_END_ADDR_BE 0x17FFF
|
||||
|
||||
Loading…
Reference in New Issue
Block a user