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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2150 v4: The v3 posting didn't do what it promised to do, so do it now for real. V3 changes: change to mov instruction (non locking instuction) instead of xchg to simplify design. V2 changes: Add xchg 16 bit instructions to handle sgdt and sidt base 63:48 bits and 47:32 bits. Add comment to explain why xchg 64bit isnt being used Split lock happens when a locking instruction is used on mis-aligned data that crosses two cachelines. If close source platform enables Alignment Check Exception(#AC), They can hit a double fault due to split lock being in CpuExceptionHandlerLib. sigt and sgdt saves 10 bytes to memory, 8 bytes is base and 2 bytes is limit. The data is mis-aligned, can cross two cacheline, and a xchg instruction(locking instuction) is being utilize. Signed-off-by: John E Lofgren <john.e.lofgren@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> |
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| .. | ||
| Ia32 | ||
| X64 | ||
| CpuExceptionCommon.c | ||
| CpuExceptionCommon.h | ||
| DxeCpuExceptionHandlerLib.inf | ||
| DxeCpuExceptionHandlerLib.uni | ||
| DxeException.c | ||
| PeiCpuException.c | ||
| PeiCpuExceptionHandlerLib.inf | ||
| PeiCpuExceptionHandlerLib.uni | ||
| PeiDxeSmmCpuException.c | ||
| SecPeiCpuException.c | ||
| SecPeiCpuExceptionHandlerLib.inf | ||
| SecPeiCpuExceptionHandlerLib.uni | ||
| SmmCpuExceptionHandlerLib.inf | ||
| SmmCpuExceptionHandlerLib.uni | ||
| SmmException.c | ||