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f15cb995bb
Cache TPM interface type info to avoid excessive interface ID register read Cc: Long Qin <qin.long@intel.com> Cc: Yao Jiewen <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chao Zhang <chao.b.zhang@intel.com> Reviewed-by: Long Qin <qin.long@intel.com>
549 lines
18 KiB
C
549 lines
18 KiB
C
/** @file
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PTP (Platform TPM Profile) CRB (Command Response Buffer) interface used by dTPM2.0 library.
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Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <IndustryStandard/Tpm20.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/IoLib.h>
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#include <Library/TimerLib.h>
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#include <Library/DebugLib.h>
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#include <Library/Tpm2DeviceLib.h>
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#include <Library/PcdLib.h>
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#include <IndustryStandard/TpmPtp.h>
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#include <IndustryStandard/TpmTis.h>
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//
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// Execution of the command may take from several seconds to minutes for certain
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// commands, such as key generation.
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//
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#define PTP_TIMEOUT_MAX (90000 * 1000) // 90s
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//
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// Max TPM command/reponse length
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//
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#define TPMCMDBUFLENGTH 0x500
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/**
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Check whether TPM PTP register exist.
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@param[in] Reg Pointer to PTP register.
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@retval TRUE TPM PTP exists.
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@retval FALSE TPM PTP is not found.
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**/
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BOOLEAN
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Tpm2IsPtpPresence (
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IN VOID *Reg
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)
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{
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UINT8 RegRead;
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RegRead = MmioRead8 ((UINTN)Reg);
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if (RegRead == 0xFF) {
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//
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// No TPM chip
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//
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return FALSE;
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}
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return TRUE;
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}
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/**
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Check whether the value of a TPM chip register satisfies the input BIT setting.
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@param[in] Register Address port of register to be checked.
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@param[in] BitSet Check these data bits are set.
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@param[in] BitClear Check these data bits are clear.
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@param[in] TimeOut The max wait time (unit MicroSecond) when checking register.
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@retval EFI_SUCCESS The register satisfies the check bit.
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@retval EFI_TIMEOUT The register can't run into the expected status in time.
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**/
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EFI_STATUS
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PtpCrbWaitRegisterBits (
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IN UINT32 *Register,
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IN UINT32 BitSet,
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IN UINT32 BitClear,
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IN UINT32 TimeOut
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)
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{
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UINT32 RegRead;
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UINT32 WaitTime;
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for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){
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RegRead = MmioRead32 ((UINTN)Register);
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if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0) {
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return EFI_SUCCESS;
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}
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MicroSecondDelay (30);
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}
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return EFI_TIMEOUT;
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}
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/**
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Get the control of TPM chip.
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@param[in] CrbReg Pointer to CRB register.
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@retval EFI_SUCCESS Get the control of TPM chip.
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@retval EFI_INVALID_PARAMETER CrbReg is NULL.
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@retval EFI_NOT_FOUND TPM chip doesn't exit.
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@retval EFI_TIMEOUT Can't get the TPM control in time.
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**/
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EFI_STATUS
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PtpCrbRequestUseTpm (
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IN PTP_CRB_REGISTERS_PTR CrbReg
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)
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{
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EFI_STATUS Status;
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if (!Tpm2IsPtpPresence (CrbReg)) {
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return EFI_NOT_FOUND;
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}
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MmioWrite32((UINTN)&CrbReg->LocalityControl, PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS);
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Status = PtpCrbWaitRegisterBits (
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&CrbReg->LocalityStatus,
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PTP_CRB_LOCALITY_STATUS_GRANTED,
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0,
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PTP_TIMEOUT_A
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);
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return Status;
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}
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/**
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Send a command to TPM for execution and return response data.
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@param[in] CrbReg TPM register space base address.
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@param[in] BufferIn Buffer for command data.
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@param[in] SizeIn Size of command data.
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@param[in, out] BufferOut Buffer for response data.
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@param[in, out] SizeOut Size of response data.
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@retval EFI_SUCCESS Operation completed successfully.
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@retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.
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@retval EFI_DEVICE_ERROR Unexpected device behavior.
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@retval EFI_UNSUPPORTED Unsupported TPM version
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**/
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EFI_STATUS
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PtpCrbTpmCommand (
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IN PTP_CRB_REGISTERS_PTR CrbReg,
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IN UINT8 *BufferIn,
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IN UINT32 SizeIn,
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IN OUT UINT8 *BufferOut,
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IN OUT UINT32 *SizeOut
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)
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{
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EFI_STATUS Status;
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UINT32 Index;
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UINT32 TpmOutSize;
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UINT16 Data16;
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UINT32 Data32;
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DEBUG_CODE (
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UINTN DebugSize;
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DEBUG ((EFI_D_VERBOSE, "PtpCrbTpmCommand Send - "));
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if (SizeIn > 0x100) {
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DebugSize = 0x40;
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} else {
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DebugSize = SizeIn;
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}
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for (Index = 0; Index < DebugSize; Index++) {
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DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));
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}
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if (DebugSize != SizeIn) {
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DEBUG ((EFI_D_VERBOSE, "...... "));
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for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {
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DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));
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}
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}
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DEBUG ((EFI_D_VERBOSE, "\n"));
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);
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TpmOutSize = 0;
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//
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// STEP 0:
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// Ready is any time the TPM is ready to receive a command, following a write
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// of 1 by software to Request.cmdReady, as indicated by the Status field
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// being cleared to 0.
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//
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MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);
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Status = PtpCrbWaitRegisterBits (
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&CrbReg->CrbControlRequest,
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0,
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PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY,
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PTP_TIMEOUT_C
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);
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if (EFI_ERROR (Status)) {
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Status = EFI_DEVICE_ERROR;
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goto Exit;
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}
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Status = PtpCrbWaitRegisterBits (
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&CrbReg->CrbControlStatus,
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0,
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PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,
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PTP_TIMEOUT_C
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);
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if (EFI_ERROR (Status)) {
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Status = EFI_DEVICE_ERROR;
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goto Exit;
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}
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//
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// STEP 1:
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// Command Reception occurs following a Ready state between the write of the
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// first byte of a command to the Command Buffer and the receipt of a write
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// of 1 to Start.
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//
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for (Index = 0; Index < SizeIn; Index++) {
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MmioWrite8 ((UINTN)&CrbReg->CrbDataBuffer[Index], BufferIn[Index]);
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}
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MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressHigh, (UINT32)RShiftU64 ((UINTN)CrbReg->CrbDataBuffer, 32));
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MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressLow, (UINT32)(UINTN)CrbReg->CrbDataBuffer);
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MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandSize, sizeof(CrbReg->CrbDataBuffer));
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MmioWrite64 ((UINTN)&CrbReg->CrbControlResponseAddrss, (UINT32)(UINTN)CrbReg->CrbDataBuffer);
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MmioWrite32 ((UINTN)&CrbReg->CrbControlResponseSize, sizeof(CrbReg->CrbDataBuffer));
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//
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// STEP 2:
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// Command Execution occurs after receipt of a 1 to Start and the TPM
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// clearing Start to 0.
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//
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MmioWrite32((UINTN)&CrbReg->CrbControlStart, PTP_CRB_CONTROL_START);
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Status = PtpCrbWaitRegisterBits (
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&CrbReg->CrbControlStart,
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0,
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PTP_CRB_CONTROL_START,
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PTP_TIMEOUT_MAX
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);
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if (EFI_ERROR (Status)) {
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//
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// Command Completion check timeout. Cancel the currently executing command by writing TPM_CRB_CTRL_CANCEL,
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// Expect TPM_RC_CANCELLED or successfully completed response.
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//
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MmioWrite32((UINTN)&CrbReg->CrbControlCancel, PTP_CRB_CONTROL_CANCEL);
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Status = PtpCrbWaitRegisterBits (
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&CrbReg->CrbControlStart,
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0,
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PTP_CRB_CONTROL_START,
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PTP_TIMEOUT_B
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);
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MmioWrite32((UINTN)&CrbReg->CrbControlCancel, 0);
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if (EFI_ERROR(Status)) {
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//
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// Still in Command Execution state. Try to goIdle, the behavior is agnostic.
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//
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Status = EFI_DEVICE_ERROR;
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goto Exit;
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}
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}
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//
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// STEP 3:
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// Command Completion occurs after completion of a command (indicated by the
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// TPM clearing TPM_CRB_CTRL_Start_x to 0) and before a write of a 1 by the
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// software to Request.goIdle.
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//
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//
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// Get response data header
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//
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for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {
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BufferOut[Index] = MmioRead8 ((UINTN)&CrbReg->CrbDataBuffer[Index]);
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}
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DEBUG_CODE (
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DEBUG ((EFI_D_VERBOSE, "PtpCrbTpmCommand ReceiveHeader - "));
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for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {
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DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));
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}
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DEBUG ((EFI_D_VERBOSE, "\n"));
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);
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//
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// Check the reponse data header (tag, parasize and returncode)
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//
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CopyMem (&Data16, BufferOut, sizeof (UINT16));
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// TPM2 should not use this RSP_COMMAND
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if (SwapBytes16 (Data16) == TPM_ST_RSP_COMMAND) {
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DEBUG ((EFI_D_ERROR, "TPM2: TPM_ST_RSP error - %x\n", TPM_ST_RSP_COMMAND));
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Status = EFI_UNSUPPORTED;
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goto Exit;
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}
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CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));
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TpmOutSize = SwapBytes32 (Data32);
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if (*SizeOut < TpmOutSize) {
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Status = EFI_BUFFER_TOO_SMALL;
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goto Exit;
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}
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*SizeOut = TpmOutSize;
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//
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// Continue reading the remaining data
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//
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for (Index = sizeof (TPM2_RESPONSE_HEADER); Index < TpmOutSize; Index++) {
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BufferOut[Index] = MmioRead8 ((UINTN)&CrbReg->CrbDataBuffer[Index]);
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}
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Exit:
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DEBUG_CODE (
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DEBUG ((EFI_D_VERBOSE, "PtpCrbTpmCommand Receive - "));
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for (Index = 0; Index < TpmOutSize; Index++) {
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DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));
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}
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DEBUG ((EFI_D_VERBOSE, "\n"));
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);
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//
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// STEP 4:
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// Idle is any time TPM_CRB_CTRL_STS_x.Status.goIdle is 1.
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//
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MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE);
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return Status;
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}
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/**
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Send a command to TPM for execution and return response data.
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@param[in] TisReg TPM register space base address.
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@param[in] BufferIn Buffer for command data.
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@param[in] SizeIn Size of command data.
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@param[in, out] BufferOut Buffer for response data.
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@param[in, out] SizeOut Size of response data.
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@retval EFI_SUCCESS Operation completed successfully.
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@retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.
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@retval EFI_DEVICE_ERROR Unexpected device behavior.
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@retval EFI_UNSUPPORTED Unsupported TPM version
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**/
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EFI_STATUS
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Tpm2TisTpmCommand (
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IN TIS_PC_REGISTERS_PTR TisReg,
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IN UINT8 *BufferIn,
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IN UINT32 SizeIn,
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IN OUT UINT8 *BufferOut,
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IN OUT UINT32 *SizeOut
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);
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/**
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Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE
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to ACCESS Register in the time of default TIS_TIMEOUT_A.
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@param[in] TisReg Pointer to TIS register.
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@retval EFI_SUCCESS Get the control of TPM chip.
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@retval EFI_INVALID_PARAMETER TisReg is NULL.
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@retval EFI_NOT_FOUND TPM chip doesn't exit.
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@retval EFI_TIMEOUT Can't get the TPM control in time.
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**/
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EFI_STATUS
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TisPcRequestUseTpm (
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IN TIS_PC_REGISTERS_PTR TisReg
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);
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/**
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Return PTP interface type.
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@param[in] Register Pointer to PTP register.
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@return PTP interface type.
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**/
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TPM2_PTP_INTERFACE_TYPE
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Tpm2GetPtpInterface (
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IN VOID *Register
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)
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{
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PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;
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PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;
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if (!Tpm2IsPtpPresence (Register)) {
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return Tpm2PtpInterfaceMax;
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}
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//
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// Check interface id
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//
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InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
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InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);
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if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB) &&
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(InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB) &&
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(InterfaceId.Bits.CapCRB != 0)) {
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return Tpm2PtpInterfaceCrb;
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}
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if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO) &&
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(InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO) &&
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(InterfaceId.Bits.CapFIFO != 0) &&
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(InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP)) {
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return Tpm2PtpInterfaceFifo;
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}
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return Tpm2PtpInterfaceTis;
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}
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/**
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Dump PTP register information.
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@param[in] Register Pointer to PTP register.
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**/
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VOID
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DumpPtpInfo (
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IN VOID *Register
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)
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{
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PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;
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PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;
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UINT8 StatusEx;
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UINT16 Vid;
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UINT16 Did;
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UINT8 Rid;
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TPM2_PTP_INTERFACE_TYPE PtpInterface;
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if (!Tpm2IsPtpPresence (Register)) {
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return ;
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}
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InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
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InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);
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StatusEx = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->StatusEx);
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//
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// Dump InterfaceId Register for PTP
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//
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DEBUG ((EFI_D_INFO, "InterfaceId - 0x%08x\n", InterfaceId.Uint32));
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DEBUG ((EFI_D_INFO, " InterfaceType - 0x%02x\n", InterfaceId.Bits.InterfaceType));
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if (InterfaceId.Bits.InterfaceType != PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS) {
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DEBUG ((EFI_D_INFO, " InterfaceVersion - 0x%02x\n", InterfaceId.Bits.InterfaceVersion));
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DEBUG ((EFI_D_INFO, " CapFIFO - 0x%x\n", InterfaceId.Bits.CapFIFO));
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DEBUG ((EFI_D_INFO, " CapCRB - 0x%x\n", InterfaceId.Bits.CapCRB));
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}
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//
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// Dump Capability Register for TIS and FIFO
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//
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DEBUG ((EFI_D_INFO, "InterfaceCapability - 0x%08x\n", InterfaceCapability.Uint32));
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if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS) ||
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(InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO)) {
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DEBUG ((EFI_D_INFO, " InterfaceVersion - 0x%x\n", InterfaceCapability.Bits.InterfaceVersion));
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}
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//
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// Dump StatusEx Register for PTP FIFO
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//
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DEBUG ((EFI_D_INFO, "StatusEx - 0x%02x\n", StatusEx));
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if (InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP) {
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DEBUG ((EFI_D_INFO, " TpmFamily - 0x%x\n", (StatusEx & PTP_FIFO_STS_EX_TPM_FAMILY) >> PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET));
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}
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Vid = 0xFFFF;
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Did = 0xFFFF;
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Rid = 0xFF;
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PtpInterface = PcdGet8(PcdActiveTpmInterfaceType);
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DEBUG ((EFI_D_INFO, "PtpInterface - %x\n", PtpInterface));
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switch (PtpInterface) {
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case Tpm2PtpInterfaceCrb:
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Vid = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Vid);
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Did = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Did);
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Rid = (UINT8)InterfaceId.Bits.Rid;
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break;
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case Tpm2PtpInterfaceFifo:
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case Tpm2PtpInterfaceTis:
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Vid = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Vid);
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Did = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Did);
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Rid = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Rid);
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break;
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default:
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break;
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}
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DEBUG ((EFI_D_INFO, "VID - 0x%04x\n", Vid));
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DEBUG ((EFI_D_INFO, "DID - 0x%04x\n", Did));
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DEBUG ((EFI_D_INFO, "RID - 0x%02x\n", Rid));
|
|
}
|
|
|
|
/**
|
|
This service enables the sending of commands to the TPM2.
|
|
|
|
@param[in] InputParameterBlockSize Size of the TPM2 input parameter block.
|
|
@param[in] InputParameterBlock Pointer to the TPM2 input parameter block.
|
|
@param[in,out] OutputParameterBlockSize Size of the TPM2 output parameter block.
|
|
@param[in] OutputParameterBlock Pointer to the TPM2 output parameter block.
|
|
|
|
@retval EFI_SUCCESS The command byte stream was successfully sent to the device and a response was successfully received.
|
|
@retval EFI_DEVICE_ERROR The command was not successfully sent to the device or a response was not successfully received from the device.
|
|
@retval EFI_BUFFER_TOO_SMALL The output parameter block is too small.
|
|
**/
|
|
EFI_STATUS
|
|
EFIAPI
|
|
DTpm2SubmitCommand (
|
|
IN UINT32 InputParameterBlockSize,
|
|
IN UINT8 *InputParameterBlock,
|
|
IN OUT UINT32 *OutputParameterBlockSize,
|
|
IN UINT8 *OutputParameterBlock
|
|
)
|
|
{
|
|
TPM2_PTP_INTERFACE_TYPE PtpInterface;
|
|
|
|
PtpInterface = PcdGet8(PcdActiveTpmInterfaceType);
|
|
switch (PtpInterface) {
|
|
case Tpm2PtpInterfaceCrb:
|
|
return PtpCrbTpmCommand (
|
|
(PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),
|
|
InputParameterBlock,
|
|
InputParameterBlockSize,
|
|
OutputParameterBlock,
|
|
OutputParameterBlockSize
|
|
);
|
|
case Tpm2PtpInterfaceFifo:
|
|
case Tpm2PtpInterfaceTis:
|
|
return Tpm2TisTpmCommand (
|
|
(TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),
|
|
InputParameterBlock,
|
|
InputParameterBlockSize,
|
|
OutputParameterBlock,
|
|
OutputParameterBlockSize
|
|
);
|
|
default:
|
|
return EFI_NOT_FOUND;
|
|
}
|
|
}
|
|
|
|
/**
|
|
This service requests use TPM2.
|
|
|
|
@retval EFI_SUCCESS Get the control of TPM2 chip.
|
|
@retval EFI_NOT_FOUND TPM2 not found.
|
|
@retval EFI_DEVICE_ERROR Unexpected device behavior.
|
|
**/
|
|
EFI_STATUS
|
|
EFIAPI
|
|
DTpm2RequestUseTpm (
|
|
VOID
|
|
)
|
|
{
|
|
TPM2_PTP_INTERFACE_TYPE PtpInterface;
|
|
|
|
PtpInterface = PcdGet8(PcdActiveTpmInterfaceType);
|
|
switch (PtpInterface) {
|
|
case Tpm2PtpInterfaceCrb:
|
|
return PtpCrbRequestUseTpm ((PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
|
|
case Tpm2PtpInterfaceFifo:
|
|
case Tpm2PtpInterfaceTis:
|
|
return TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
|
|
default:
|
|
return EFI_NOT_FOUND;
|
|
}
|
|
}
|