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Also add ExceptionList in MdeModulePkg\MdeModulePkg.ci.yaml, to avoid open CI issue, because UID and HID are terms which are already used in current source code. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
92 lines
5.3 KiB
C
92 lines
5.3 KiB
C
/** @file
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This file defines the structure for the PCI Root Bridges.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Revision Reference:
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- Universal Payload Specification 0.75 (https://universalpayload.github.io/documentation/)
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**/
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#ifndef UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H_
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#define UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H_
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#include <UniversalPayload/UniversalPayload.h>
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#pragma pack(1)
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//
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// (Base > Limit) indicates an aperture is not available.
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//
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typedef struct {
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//
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// Base and Limit are the device address instead of host address when
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// Translation is not zero
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//
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UINT64 Base;
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UINT64 Limit;
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//
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// According to UEFI 2.7, Device Address = Host Address + Translation,
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// so Translation = Device Address - Host Address.
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// On platforms where Translation is not zero, the subtraction is probably to
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// be performed with UINT64 wrap-around semantics, for we may translate an
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// above-4G host address into a below-4G device address for legacy PCIe device
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// compatibility.
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//
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// NOTE: The alignment of Translation is required to be larger than any BAR
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// alignment in the same root bridge, so that the same alignment can be
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// applied to both device address and host address, which simplifies the
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// situation and makes the current resource allocation code in generic PCI
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// host bridge driver still work.
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//
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UINT64 Translation;
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} UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE;
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///
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/// Payload PCI Root Bridge Information HOB
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///
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typedef struct {
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UINT32 Segment; ///< Segment number.
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UINT64 Supports; ///< Supported attributes.
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///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()
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///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
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UINT64 Attributes; ///< Initial attributes.
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///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()
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///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
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BOOLEAN DmaAbove4G; ///< DMA above 4GB memory.
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///< Set to TRUE when root bridge supports DMA above 4GB memory.
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BOOLEAN NoExtendedConfigSpace; ///< When FALSE, the root bridge supports
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///< Extended (4096-byte) Configuration Space.
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///< When TRUE, the root bridge supports
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///< 256-byte Configuration Space only.
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UINT64 AllocationAttributes; ///< Allocation attributes.
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///< Refer to EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM and
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///< EFI_PCI_HOST_BRIDGE_MEM64_DECODE used by GetAllocAttributes()
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///< in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
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UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Bus; ///< Bus aperture which can be used by the root bridge.
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UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Io; ///< IO aperture which can be used by the root bridge.
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UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Mem; ///< MMIO aperture below 4GB which can be used by the root bridge.
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UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE MemAbove4G; ///< MMIO aperture above 4GB which can be used by the root bridge.
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UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMem; ///< Prefetchable MMIO aperture below 4GB which can be used by the root bridge.
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UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; ///< Prefetchable MMIO aperture above 4GB which can be used by the root bridge.
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UINT32 HID; ///< PnP hardware ID of the root bridge. This value must match the corresponding
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///< _HID in the ACPI name space.
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UINT32 UID; ///< Unique ID that is required by ACPI if two devices have the same _HID.
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///< This value must also match the corresponding _UID/_HID pair in the ACPI name space.
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} UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE;
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typedef struct {
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UNIVERSAL_PAYLOAD_GENERIC_HEADER Header;
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BOOLEAN ResourceAssigned;
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UINT8 Count;
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UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE RootBridge[0];
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} UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES;
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#pragma pack()
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#define UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_REVISION 1
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extern GUID gUniversalPayloadPciRootBridgeInfoGuid;
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#endif // UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H_
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