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7ede80607b
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Qian Yi <yi.qian@intel.com> Reviewed-by: Zailing Sun <zailiang.sun@intel.com>
105 lines
2.5 KiB
C
105 lines
2.5 KiB
C
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/*++
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Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved
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SPDX-License-Identifier: BSD-2-Clause-Patent
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Module Name:
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VlvPolicy.h
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Abstract:
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Interface definition details between ValleyView MRC and platform drivers during PEI phase.
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--*/
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#ifndef _VLV_POLICY_PPI_H_
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#define _VLV_POLICY_PPI_H_
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//
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// MRC Policy provided by platform for PEI phase {7D84B2C2-22A1-4372-B12C-EBB232D3A6A3}
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//
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#define VLV_POLICY_PPI_GUID \
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{ \
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0x7D84B2C2, 0x22A1, 0x4372, 0xB1, 0x2C, 0xEB, 0xB2, 0x32, 0xD3, 0xA6, 0xA3 \
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}
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//
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// Extern the GUID for protocol users.
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//
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extern EFI_GUID gVlvPolicyPpiGuid;
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//
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// PPI revision number
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// Any backwards compatible changes to this PPI will result in an update in the revision number
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// Major changes will require publication of a new PPI
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//
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#define MRC_PLATFORM_POLICY_PPI_REVISION 1
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#ifndef MAX_SOCKETS
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#define MAX_SOCKETS 4
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#endif
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#define S3_TIMING_DATA_LEN 9
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#define S3_READ_TRAINING_DATA_LEN 16
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#define S3_WRITE_TRAINING_DATA_LEN 12
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#ifndef S3_RESTORE_DATA_LEN
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#define S3_RESTORE_DATA_LEN (S3_TIMING_DATA_LEN + S3_READ_TRAINING_DATA_LEN + S3_WRITE_TRAINING_DATA_LEN)
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#endif // S3_RESTORE_DATA_LEN
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#pragma pack(1)
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//
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// MRC Platform Data Structure
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//
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typedef struct {
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UINT8 SpdAddressTable[MAX_SOCKETS];
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UINT8 TSonDimmSmbusAddress[MAX_SOCKETS];
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UINT16 SmbusBar;
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UINT32 IchRcba;
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UINT32 WdbBaseAddress; // Write Data Buffer area (WC caching mode)
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UINT32 WdbRegionSize;
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UINT32 SmBusAddress;
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UINT8 UserBd;
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UINT8 PlatformType;
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UINT8 FastBoot;
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UINT8 DynSR;
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} VLV_PLATFORM_DATA;
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typedef struct {
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UINT16 MmioSize;
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UINT16 GttSize;
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UINT8 IgdDvmt50PreAlloc;
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UINT8 PrimaryDisplay;
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UINT8 PAVPMode;
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UINT8 ApertureSize;
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} GT_CONFIGURATION;
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typedef struct {
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UINT8 EccSupport;
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UINT16 DdrFreqLimit;
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UINT8 MaxTolud;
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} MEMORY_CONFIGURATION;
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//
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// MRC Platform Policiy PPI
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//
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typedef struct _VLV_POLICY_PPI {
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UINT8 Revision;
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VLV_PLATFORM_DATA PlatformData;
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GT_CONFIGURATION GtConfig;
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MEMORY_CONFIGURATION MemConfig;
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VOID *S3DataPtr; // was called MRC_PARAMS_SAVE_RESTORE
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UINT8 ISPEn; //ISP (IUNIT) Device Enabled
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UINT8 ISPPciDevConfig; //ISP (IUNIT) Device Config: 0->B0/D2/F0 for Window OS, 1->B0D3/F0 for Linux OS
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} VLV_POLICY_PPI;
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#pragma pack()
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#endif // _VLV_POLICY_PPI_H_
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