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7ede80607b
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Qian Yi <yi.qian@intel.com> Reviewed-by: Zailing Sun <zailiang.sun@intel.com>
40 lines
2.4 KiB
Plaintext
40 lines
2.4 KiB
Plaintext
/**************************************************************************;
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;* *;
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;* *;
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;* Intel Corporation - ACPI Reference Code for the Sandy Bridge *;
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;* Family of Customer Reference Boards. *;
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;* *;
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;* *;
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;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;
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;
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;* *;
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;* *;
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;**************************************************************************/
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Name(PMBS, 0x400) // ASL alias for ACPI I/O base address.
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Name(SMIP, 0xb2) // I/O port to trigger SMI
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Name(GPBS, 0x500) // GPIO Register Block address
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Name(APCB, 0xfec00000) // Default I/O APIC(s) memory start address, 0x0FEC00000 - default, 0 - I/O APIC's disabled
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Name(APCL, 0x1000) // I/O APIC(s) memory decoded range, 0x1000 - default, 0 - I/O APIC's not decoded
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Name(PFDR, 0xfed03034) // PMC Function Disable Register
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Name(PMCB, 0xfed03000) // PMC Base Address
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Name(PCLK, 0xfed03060) // PMC Clock Control Register
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Name(PUNB, 0xfed05000) // PUNIT Base Address
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Name(IBAS, 0xfed08000) // ILB Base Address
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Name(SRCB, 0xfed1c000) // RCBA (Root Complex Base Address)
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Name(SRCL, 0x1000) // RCBA length
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Name(HPTB, 0xfed00000) // Same as HPET_BASE_ADDRESS for ASL use
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Name(PEBS, 0xe0000000) // PCIe Base
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Name(PELN, 0x10000000) //
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Name(FMBL, 0x1) // Platform Flavor - Mobile flavor for ASL code.
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Name(FDTP, 0x2) // Platform Flavor - Desktop flavor for ASL code.
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Name(SDGV, 0x1c) // UHCI Controller HOST_ALERT's bit offset within the GPE block. GPIO[0:15] corresponding to GPE[16:31]
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Name(PEHP, 0x1) // _OSC: Pci Express Native Hot Plug Control
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Name(SHPC, 0x0) // _OSC: Standard Hot Plug Controller (SHPC) Native Hot Plug control
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Name(PEPM, 0x1) // _OSC: Pci Express Native Power Management Events control
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Name(PEER, 0x1) // _OSC: Pci Express Advanced Error Reporting control
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Name(PECS, 0x1) // _OSC: Pci Express Capability Structure control
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