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	2. Update Capsule modules to consume debug agent library to support source debugging in x64 code. 3. Update BootScriptExecutorDxe module to support source debugging on S3 path. signed-off-by: Jeff Fan <jeff.fan@intel.com> reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13680 6f19259b-4bc3-4df7-8a09-765794883524
		
			
				
	
	
		
			131 lines
		
	
	
		
			5.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			131 lines
		
	
	
		
			5.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/** @file
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Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions
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of the BSD License which accompanies this distribution.  The
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full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _CAPSULE_PEIM_H_
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#define _CAPSULE_PEIM_H_
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#include <PiPei.h>
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#include <Uefi/UefiSpec.h>
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#include <Ppi/Capsule.h>
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#include <Ppi/LoadFile.h>
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#include <Ppi/ReadOnlyVariable2.h>
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#include <Guid/CapsuleVendor.h>
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#include <Library/DebugLib.h>
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#include <Library/PeimEntryPoint.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/HobLib.h>
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#include <Library/PeiServicesTablePointerLib.h>
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#include <Library/PrintLib.h>
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#include <Library/PeCoffLib.h>
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#include <Library/PeCoffGetEntryPointLib.h>
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#include <Library/PcdLib.h>
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#include <Library/ReportStatusCodeLib.h>
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#include <Library/DebugAgentLib.h>
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#include <IndustryStandard/PeImage.h>
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#include "Common/CommonHeader.h"
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#ifdef MDE_CPU_IA32 
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#pragma pack(1)
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//
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// Page-Map Level-4 Offset (PML4) and
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// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
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//
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typedef union {
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  struct {
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    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
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    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
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    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
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    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
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    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
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    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
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    UINT64  Reserved:1;               // Reserved
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    UINT64  MustBeZero:2;             // Must Be Zero
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    UINT64  Available:3;              // Available for use by system software
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    UINT64  PageTableBaseAddress:40;  // Page Table Base Address
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    UINT64  AvabilableHigh:11;        // Available for use by system software
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    UINT64  Nx:1;                     // No Execute bit
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  } Bits;
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  UINT64    Uint64;
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} PAGE_MAP_AND_DIRECTORY_POINTER;
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//
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// Page Table Entry 2MB
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//
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typedef union {
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  struct {
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    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
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    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
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    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
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    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
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    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
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    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
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    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
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    UINT64  MustBe1:1;                // Must be 1 
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    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
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    UINT64  Available:3;              // Available for use by system software
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    UINT64  PAT:1;                    //
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    UINT64  MustBeZero:8;             // Must be zero;
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    UINT64  PageTableBaseAddress:31;  // Page Table Base Address
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    UINT64  AvabilableHigh:11;        // Available for use by system software
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    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
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  } Bits;
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  UINT64    Uint64;
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} PAGE_TABLE_ENTRY;
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//
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// Page Table Entry 1GB
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//
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typedef union {
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  struct {
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    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
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    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
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    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
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    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
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    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
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    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
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    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
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    UINT64  MustBe1:1;                // Must be 1 
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    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
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    UINT64  Available:3;              // Available for use by system software
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    UINT64  PAT:1;                    //
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    UINT64  MustBeZero:17;            // Must be zero;
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    UINT64  PageTableBaseAddress:22;  // Page Table Base Address
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    UINT64  AvabilableHigh:11;        // Available for use by system software
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    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
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  } Bits;
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  UINT64    Uint64;
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} PAGE_TABLE_1G_ENTRY;
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#pragma pack()
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typedef
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EFI_STATUS
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(*COALESCE_ENTRY) (
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  IN EFI_PEI_SERVICES                **PeiServices,
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  IN EFI_CAPSULE_BLOCK_DESCRIPTOR    *BlockList,
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  IN OUT VOID                        **MemoryBase,
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  IN OUT UINTN                       *MemorySize
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  );
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#endif
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#endif
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