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9344f09215
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
339 lines
16 KiB
C
339 lines
16 KiB
C
/** @file
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This file declares PlatfromOpRom protocols that provide the interface between
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the PCI bus driver/PCI Host Bridge Resource Allocation driver and a platform-specific
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driver to describe the unique features of a platform.
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This protocol is optional.
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Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Revision Reference:
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This Protocol is defined in UEFI Platform Initialization Specification 1.2
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Volume 5: Standards
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**/
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#ifndef _PCI_PLATFORM_H_
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#define _PCI_PLATFORM_H_
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///
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/// This file must be included because the EFI_PCI_PLATFORM_PROTOCOL uses
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/// EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE.
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///
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#include <Protocol/PciHostBridgeResourceAllocation.h>
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///
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/// Global ID for the EFI_PCI_PLATFORM_PROTOCOL.
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///
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#define EFI_PCI_PLATFORM_PROTOCOL_GUID \
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{ \
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0x7d75280, 0x27d4, 0x4d69, {0x90, 0xd0, 0x56, 0x43, 0xe2, 0x38, 0xb3, 0x41} \
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}
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///
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/// Forward declaration for EFI_PCI_PLATFORM_PROTOCOL.
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///
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typedef struct _EFI_PCI_PLATFORM_PROTOCOL EFI_PCI_PLATFORM_PROTOCOL;
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///
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/// EFI_PCI_PLATFORM_POLICY that is a bitmask with the following legal combinations:
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/// - EFI_RESERVE_NONE_IO_ALIAS:<BR>
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/// Does not set aside either ISA or VGA I/O resources during PCI
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/// enumeration. By using this selection, the platform indicates that it does
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/// not want to support a PCI device that requires ISA or legacy VGA
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/// resources. If a PCI device driver asks for these resources, the request
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/// will be turned down.
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/// - EFI_RESERVE_ISA_IO_ALIAS | EFI_RESERVE_VGA_IO_ALIAS:<BR>
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/// Sets aside the ISA I/O range and all the aliases during PCI
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/// enumeration. VGA I/O ranges and aliases are included in ISA alias
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/// ranges. In this scheme, seventy-five percent of the I/O space remains unused.
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/// By using this selection, the platform indicates that it wants to support
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/// PCI devices that require the following, at the cost of wasted I/O space:
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/// ISA range and its aliases
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/// Legacy VGA range and its aliases
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/// The PCI bus driver will not allocate I/O addresses out of the ISA I/O
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/// range and its aliases. The following are the ISA I/O ranges:
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/// - n100..n3FF
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/// - n500..n7FF
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/// - n900..nBFF
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/// - nD00..nFFF
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///
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/// In this case, the PCI bus driver will ask the PCI host bridge driver for
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/// larger I/O ranges. The PCI host bridge driver is not aware of the ISA
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/// aliasing policy and merely attempts to allocate the requested ranges.
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/// The first device that requests the legacy VGA range will get all the
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/// legacy VGA range plus its aliased addresses forwarded to it. The first
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/// device that requests the legacy ISA range will get all the legacy ISA
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/// range, plus its aliased addresses, forwarded to it.
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/// - EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_ALIAS:<BR>
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/// Sets aside the ISA I/O range (0x100 - 0x3FF) during PCI enumeration
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/// and the aliases of the VGA I/O ranges. By using this selection, the
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/// platform indicates that it will support VGA devices that require VGA
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/// ranges, including those that require VGA aliases. The platform further
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/// wants to support non-VGA devices that ask for the ISA range (0x100 -
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/// 3FF), but not if it also asks for the ISA aliases. The PCI bus driver will
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/// not allocate I/O addresses out of the legacy ISA I/O range (0x100 -
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/// 0x3FF) range or the aliases of the VGA I/O range. If a PCI device
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/// driver asks for the ISA I/O ranges, including aliases, the request will be
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/// turned down. The first device that requests the legacy VGA range will
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/// get all the legacy VGA range plus its aliased addresses forwarded to
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/// it. When the legacy VGA device asks for legacy VGA ranges and its
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/// aliases, all the upstream PCI-to-PCI bridges must be set up to perform
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/// 10-bit decode on legacy VGA ranges. To prevent two bridges from
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/// positively decoding the same address, all PCI-to-PCI bridges that are
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/// peers to this bridge will have to be set up to not decode ISA aliased
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/// ranges. In that case, all the devices behind the peer bridges can
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/// occupy only I/O addresses that are not ISA aliases. This is a limitation
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/// of PCI-to-PCI bridges and is described in the white paper PCI-to-PCI
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/// Bridges and Card Bus Controllers on Windows 2000, Windows XP,
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/// and Windows Server 2003. The PCI enumeration process must be
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/// cognizant of this restriction.
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/// - EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO_ALIAS:<BR>
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/// Sets aside the ISA I/O range (0x100 - 0x3FF) during PCI enumeration.
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/// VGA I/O ranges are included in the ISA range. By using this selection,
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/// the platform indicates that it wants to support PCI devices that require
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/// the ISA range and legacy VGA range, but it does not want to support
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/// devices that require ISA alias ranges or VGA alias ranges. The PCI
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/// bus driver will not allocate I/O addresses out of the legacy ISA I/O
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/// range (0x100-0x3FF). If a PCI device driver asks for the ISA I/O
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/// ranges, including aliases, the request will be turned down. By using
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/// this selection, the platform indicates that it will support VGA devices
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/// that require VGA ranges, but it will not support VGA devices that
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/// require VGA aliases. To truly support 16-bit VGA decode, all the PCIto-
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/// PCI bridges that are upstream to a VGA device, as well as
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/// upstream to the parent PCI root bridge, must support 16-bit VGA I/O
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/// decode. See the PCI-to-PCI Bridge Architecture Specification for
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/// information regarding the 16-bit VGA decode support. This
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/// requirement must hold true for every VGA device in the system. If any
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/// of these bridges does not support 16-bit VGA decode, it will positively
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/// decode all the aliases of the VGA I/O ranges and this selection must
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/// be treated like EFI_RESERVE_ISA_IO_NO_ALIAS |
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/// EFI_RESERVE_VGA_IO_ALIAS.
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///
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typedef UINT32 EFI_PCI_PLATFORM_POLICY;
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///
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/// Does not set aside either ISA or VGA I/O resources during PCI
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/// enumeration.
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///
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#define EFI_RESERVE_NONE_IO_ALIAS 0x0000
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///
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/// Sets aside ISA I/O range and all aliases:
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/// - n100..n3FF
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/// - n500..n7FF
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/// - n900..nBFF
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/// - nD00..nFFF.
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///
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#define EFI_RESERVE_ISA_IO_ALIAS 0x0001
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///
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/// Sets aside ISA I/O range 0x100-0x3FF.
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///
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#define EFI_RESERVE_ISA_IO_NO_ALIAS 0x0002
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///
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/// Sets aside VGA I/O ranges and all aliases.
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///
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#define EFI_RESERVE_VGA_IO_ALIAS 0x0004
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///
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/// Sets aside VGA I/O ranges
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///
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#define EFI_RESERVE_VGA_IO_NO_ALIAS 0x0008
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///
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/// EFI_PCI_EXECUTION_PHASE is used to call a platform protocol and execute
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/// platform-specific code.
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///
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typedef enum {
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///
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/// The phase that indicates the entry point to the PCI Bus Notify phase. This
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/// platform hook is called before the PCI bus driver calls the
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/// EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL driver.
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///
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BeforePciHostBridge = 0,
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///
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/// The phase that indicates the entry point to the PCI Bus Notify phase. This
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/// platform hook is called before the PCI bus driver calls the
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/// EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL driver.
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///
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ChipsetEntry = 0,
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///
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/// The phase that indicates the exit point to the Chipset Notify phase before
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/// returning to the PCI Bus Driver Notify phase. This platform hook is called after
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/// the PCI bus driver calls the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
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/// driver.
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///
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AfterPciHostBridge = 1,
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///
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/// The phase that indicates the exit point to the Chipset Notify phase before
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/// returning to the PCI Bus Driver Notify phase. This platform hook is called after
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/// the PCI bus driver calls the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
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/// driver.
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///
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ChipsetExit = 1,
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MaximumChipsetPhase
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} EFI_PCI_EXECUTION_PHASE;
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typedef EFI_PCI_EXECUTION_PHASE EFI_PCI_CHIPSET_EXECUTION_PHASE;
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/**
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The notification from the PCI bus enumerator to the platform that it is
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about to enter a certain phase during the enumeration process.
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The PlatformNotify() function can be used to notify the platform driver so that
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it can perform platform-specific actions. No specific actions are required.
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Eight notification points are defined at this time. More synchronization points
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may be added as required in the future. The PCI bus driver calls the platform driver
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twice for every Phase-once before the PCI Host Bridge Resource Allocation Protocol
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driver is notified, and once after the PCI Host Bridge Resource Allocation Protocol
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driver has been notified.
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This member function may not perform any error checking on the input parameters. It
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also does not return any error codes. If this member function detects any error condition,
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it needs to handle those errors on its own because there is no way to surface any
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errors to the caller.
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@param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.
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@param[in] HostBridge The handle of the host bridge controller.
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@param[in] Phase The phase of the PCI bus enumeration.
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@param[in] ExecPhase Defines the execution phase of the PCI chipset driver.
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@retval EFI_SUCCESS The function completed successfully.
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**/
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typedef
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EFI_STATUS
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(EFIAPI *EFI_PCI_PLATFORM_PHASE_NOTIFY)(
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IN EFI_PCI_PLATFORM_PROTOCOL *This,
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IN EFI_HANDLE HostBridge,
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IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase,
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IN EFI_PCI_EXECUTION_PHASE ExecPhase
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);
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/**
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The notification from the PCI bus enumerator to the platform for each PCI
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controller at several predefined points during PCI controller initialization.
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The PlatformPrepController() function can be used to notify the platform driver so that
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it can perform platform-specific actions. No specific actions are required.
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Several notification points are defined at this time. More synchronization points may be
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added as required in the future. The PCI bus driver calls the platform driver twice for
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every PCI controller-once before the PCI Host Bridge Resource Allocation Protocol driver
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is notified, and once after the PCI Host Bridge Resource Allocation Protocol driver has
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been notified.
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This member function may not perform any error checking on the input parameters. It also
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does not return any error codes. If this member function detects any error condition, it
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needs to handle those errors on its own because there is no way to surface any errors to
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the caller.
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@param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.
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@param[in] HostBridge The associated PCI host bridge handle.
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@param[in] RootBridge The associated PCI root bridge handle.
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@param[in] PciAddress The address of the PCI device on the PCI bus.
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@param[in] Phase The phase of the PCI controller enumeration.
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@param[in] ExecPhase Defines the execution phase of the PCI chipset driver.
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@retval EFI_SUCCESS The function completed successfully.
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**/
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typedef
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EFI_STATUS
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(EFIAPI *EFI_PCI_PLATFORM_PREPROCESS_CONTROLLER)(
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IN EFI_PCI_PLATFORM_PROTOCOL *This,
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IN EFI_HANDLE HostBridge,
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IN EFI_HANDLE RootBridge,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
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IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase,
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IN EFI_PCI_EXECUTION_PHASE ExecPhase
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);
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/**
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Retrieves the platform policy regarding enumeration.
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The GetPlatformPolicy() function retrieves the platform policy regarding PCI
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enumeration. The PCI bus driver and the PCI Host Bridge Resource Allocation Protocol
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driver can call this member function to retrieve the policy.
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@param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.
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@param[out] PciPolicy The platform policy with respect to VGA and ISA aliasing.
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@retval EFI_SUCCESS The function completed successfully.
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@retval EFI_INVALID_PARAMETER PciPolicy is NULL.
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**/
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typedef
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EFI_STATUS
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(EFIAPI *EFI_PCI_PLATFORM_GET_PLATFORM_POLICY)(
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IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,
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OUT EFI_PCI_PLATFORM_POLICY *PciPolicy
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);
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/**
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Gets the PCI device's option ROM from a platform-specific location.
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The GetPciRom() function gets the PCI device's option ROM from a platform-specific location.
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The option ROM will be loaded into memory. This member function is used to return an image
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that is packaged as a PCI 2.2 option ROM. The image may contain both legacy and EFI option
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ROMs. See the UEFI 2.0 Specification for details. This member function can be used to return
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option ROM images for embedded controllers. Option ROMs for embedded controllers are typically
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stored in platform-specific storage, and this member function can retrieve it from that storage
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and return it to the PCI bus driver. The PCI bus driver will call this member function before
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scanning the ROM that is attached to any controller, which allows a platform to specify a ROM
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image that is different from the ROM image on a PCI card.
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@param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.
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@param[in] PciHandle The handle of the PCI device.
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@param[out] RomImage If the call succeeds, the pointer to the pointer to the option ROM image.
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Otherwise, this field is undefined. The memory for RomImage is allocated
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by EFI_PCI_PLATFORM_PROTOCOL.GetPciRom() using the EFI Boot Service AllocatePool().
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It is the caller's responsibility to free the memory using the EFI Boot Service
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FreePool(), when the caller is done with the option ROM.
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@param[out] RomSize If the call succeeds, a pointer to the size of the option ROM size. Otherwise,
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this field is undefined.
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@retval EFI_SUCCESS The option ROM was available for this device and loaded into memory.
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@retval EFI_NOT_FOUND No option ROM was available for this device.
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@retval EFI_OUT_OF_RESOURCES No memory was available to load the option ROM.
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@retval EFI_DEVICE_ERROR An error occurred in obtaining the option ROM.
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**/
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typedef
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EFI_STATUS
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(EFIAPI *EFI_PCI_PLATFORM_GET_PCI_ROM)(
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IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,
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IN EFI_HANDLE PciHandle,
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OUT VOID **RomImage,
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OUT UINTN *RomSize
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);
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///
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/// This protocol provides the interface between the PCI bus driver/PCI Host
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/// Bridge Resource Allocation driver and a platform-specific driver to describe
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/// the unique features of a platform.
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///
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struct _EFI_PCI_PLATFORM_PROTOCOL {
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///
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/// The notification from the PCI bus enumerator to the platform that it is about to
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/// enter a certain phase during the enumeration process.
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///
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EFI_PCI_PLATFORM_PHASE_NOTIFY PlatformNotify;
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///
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/// The notification from the PCI bus enumerator to the platform for each PCI
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/// controller at several predefined points during PCI controller initialization.
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///
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EFI_PCI_PLATFORM_PREPROCESS_CONTROLLER PlatformPrepController;
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///
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/// Retrieves the platform policy regarding enumeration.
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///
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EFI_PCI_PLATFORM_GET_PLATFORM_POLICY GetPlatformPolicy;
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///
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/// Gets the PCI device's option ROM from a platform-specific location.
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///
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EFI_PCI_PLATFORM_GET_PCI_ROM GetPciRom;
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};
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extern EFI_GUID gEfiPciPlatformProtocolGuid;
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#endif
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