Abner Chang ea56fa3d47 BaseTools: Enable RISC-V architecture for RISC-V EDK2 CI. ... BZ:2562: https://bugzilla.tianocore.org/show_bug.cgi?id=2562 EDK CI for RISC-V architecture Enable RISC-V architecture for RISC-V EDK2 CI testing. Signed-off-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bob Feng <bob.c.feng@intel.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Gilbert Chen <gilbert.chen@hpe.com> Cc: Daniel Helmut Schaefer <daniel.schaefer@hpe.com>		2020-05-07 03:17:15 +00:00
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LinuxGcc5ToolChain_plug_in.yaml	BaseTools: Add BaseTools plugins to support CI	2019-11-11 13:01:58 -08:00
LinuxGcc5ToolChain.py	BaseTools: Enable RISC-V architecture for RISC-V EDK2 CI.	2020-05-07 03:17:15 +00:00