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	 4059386c70
			
		
	
	
		4059386c70
		
	
	
	
	
		
			
			https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
		
			
				
	
	
		
			46 lines
		
	
	
		
			1.1 KiB
		
	
	
	
		
			ArmAsm
		
	
	
	
	
	
			
		
		
	
	
			46 lines
		
	
	
		
			1.1 KiB
		
	
	
	
		
			ArmAsm
		
	
	
	
	
	
| //
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| //  Copyright (c) 2012-2014, ARM Limited. All rights reserved.
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| //  Copyright (c) 2014-2016, Linaro Limited. All rights reserved.
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| //
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| //  SPDX-License-Identifier: BSD-2-Clause-Patent
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| //
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| //
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| 
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| #include <AsmMacroIoLib.h>
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| 
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| .arch_extension virt
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| 
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| ASM_FUNC(ArmCallHvc)
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|     push    {r4-r8}
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|     // r0 will be popped just after the HVC call
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|     push    {r0}
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| 
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|     // Load the HVC arguments values into the appropriate registers
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|     ldr     r7, [r0, #28]
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|     ldr     r6, [r0, #24]
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|     ldr     r5, [r0, #20]
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|     ldr     r4, [r0, #16]
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|     ldr     r3, [r0, #12]
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|     ldr     r2, [r0, #8]
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|     ldr     r1, [r0, #4]
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|     ldr     r0, [r0, #0]
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| 
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|     hvc     #0
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| 
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|     // Pop the ARM_HVC_ARGS structure address from the stack into r8
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|     pop     {r8}
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| 
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|     // Load the HVC returned values into the appropriate registers
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|     // A HVC call can return up to 4 values - we do not need to store back r4-r7.
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|     str     r3, [r8, #12]
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|     str     r2, [r8, #8]
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|     str     r1, [r8, #4]
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|     str     r0, [r8, #0]
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| 
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|     mov     r0, r8
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| 
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|     // Restore the registers r4-r8
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|     pop     {r4-r8}
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| 
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|     bx      lr
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