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09943f5ecc
Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13226 6f19259b-4bc3-4df7-8a09-765794883524
364 lines
9.4 KiB
C
364 lines
9.4 KiB
C
/** @file
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This file contains the definination for host controller register operation routines.
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Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _EFI_EHCI_REG_H_
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#define _EFI_EHCI_REG_H_
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//
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// EHCI register offset
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//
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//
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// Capability register offset
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//
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#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
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#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h
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#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset
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//
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// Capability register bit definition
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//
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#define HCSP_NPORTS 0x0F // Number of root hub port
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#define HCSP_PPC 0x10 // Port Power Control
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#define HCCP_64BIT 0x01 // 64-bit addressing capability
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//
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// Operational register offset
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//
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#define EHC_USBCMD_OFFSET 0x0 // USB command register offset
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#define EHC_USBSTS_OFFSET 0x04 // Statue register offset
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#define EHC_USBINTR_OFFSET 0x08 // USB interrutp offset
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#define EHC_FRINDEX_OFFSET 0x0C // Frame index offset
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#define EHC_CTRLDSSEG_OFFSET 0x10 // Control data structure segment offset
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#define EHC_FRAME_BASE_OFFSET 0x14 // Frame list base address offset
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#define EHC_ASYNC_HEAD_OFFSET 0x18 // Next asynchronous list address offset
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#define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset
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#define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset
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#define EHC_FRAME_LEN 1024
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//
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// Register bit definition
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//
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#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC
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#define USBCMD_RUN 0x01 // Run/stop
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#define USBCMD_RESET 0x02 // Start the host controller reset
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#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule
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#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule
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#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell
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#define USBSTS_IAA 0x20 // Interrupt on async advance
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#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status
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#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status
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#define USBSTS_HALT 0x1000 // Host controller halted
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#define USBSTS_SYS_ERROR 0x10 // Host system error
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#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC
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// (write clean) bits in USBSTS register
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#define PORTSC_CONN 0x01 // Current Connect Status
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#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change
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#define PORTSC_ENABLED 0x04 // Port Enable / Disable
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#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change
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#define PORTSC_OVERCUR 0x10 // Over current Active
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#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change
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#define PORSTSC_RESUME 0x40 // Force Port Resume
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#define PORTSC_SUSPEND 0x80 // Port Suspend State
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#define PORTSC_RESET 0x100 // Port Reset
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#define PORTSC_LINESTATE_K 0x400 // Line Status K-state
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#define PORTSC_LINESTATE_J 0x800 // Line Status J-state
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#define PORTSC_POWER 0x1000 // Port Power
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#define PORTSC_OWNER 0x2000 // Port Owner
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#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,
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// they are WC (write clean)
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//
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// PCI Configuration Registers
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//
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#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10
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//
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// Debug port capability id
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//
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#define EHC_DEBUG_PORT_CAP_ID 0x0A
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#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
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#define EHC_ADDR(High, QhHw32) \
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((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))
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#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
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//
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// Structure to map the hardware port states to the
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// UEFI's port states.
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//
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typedef struct {
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UINT16 HwState;
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UINT16 UefiState;
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} USB_PORT_STATE_MAP;
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//
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// Ehci Data and Ctrl Structures
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//
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#pragma pack(1)
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typedef struct {
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UINT8 ProgInterface;
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UINT8 SubClassCode;
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UINT8 BaseCode;
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} USB_CLASSC;
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#pragma pack()
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/**
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Read EHCI capability register.
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@param Ehc The EHCI device.
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@param Offset Capability register address.
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@return The register content.
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**/
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UINT32
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EhcReadCapRegister (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Offset
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);
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/**
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Read EHCI debug port register.
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@param Ehc The EHCI device.
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@param Offset Debug port register address.
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@return The register content read.
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@retval If err, return 0xffff.
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**/
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UINT32
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EhcReadDbgRegister (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Offset
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);
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/**
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Read EHCI Operation register.
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@param Ehc The EHCI device.
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@param Offset The operation register offset.
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@return The register content.
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**/
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UINT32
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EhcReadOpReg (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Offset
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);
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/**
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Write the data to the EHCI operation register.
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@param Ehc The EHCI device.
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@param Offset EHCI operation register offset.
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@param Data The data to write.
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**/
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VOID
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EhcWriteOpReg (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Offset,
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IN UINT32 Data
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);
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/**
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Set one bit of the operational register while keeping other bits.
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@param Ehc The EHCI device.
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@param Offset The offset of the operational register.
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@param Bit The bit mask of the register to set.
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**/
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VOID
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EhcSetOpRegBit (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Offset,
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IN UINT32 Bit
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);
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/**
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Clear one bit of the operational register while keeping other bits.
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@param Ehc The EHCI device.
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@param Offset The offset of the operational register.
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@param Bit The bit mask of the register to clear.
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**/
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VOID
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EhcClearOpRegBit (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Offset,
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IN UINT32 Bit
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);
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/**
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Add support for UEFI Over Legacy (UoL) feature, stop
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the legacy USB SMI support.
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@param Ehc The EHCI device.
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**/
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VOID
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EhcClearLegacySupport (
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IN USB2_HC_DEV *Ehc
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);
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/**
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Set door bell and wait it to be ACKed by host controller.
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This function is used to synchronize with the hardware.
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@param Ehc The EHCI device.
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@param Timeout The time to wait before abort (in millisecond, ms).
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@retval EFI_SUCCESS Synchronized with the hardware.
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@retval EFI_TIMEOUT Time out happened while waiting door bell to set.
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**/
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EFI_STATUS
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EhcSetAndWaitDoorBell (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Timeout
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);
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/**
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Clear all the interrutp status bits, these bits are Write-Clean.
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@param Ehc The EHCI device.
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**/
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VOID
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EhcAckAllInterrupt (
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IN USB2_HC_DEV *Ehc
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);
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/**
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Whether Ehc is halted.
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@param Ehc The EHCI device.
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@retval TRUE The controller is halted.
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@retval FALSE It isn't halted.
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**/
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BOOLEAN
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EhcIsHalt (
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IN USB2_HC_DEV *Ehc
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);
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/**
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Whether system error occurred.
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@param Ehc The EHCI device.
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@retval TRUE System error happened.
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@retval FALSE No system error.
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**/
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BOOLEAN
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EhcIsSysError (
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IN USB2_HC_DEV *Ehc
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);
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/**
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Reset the host controller.
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@param Ehc The EHCI device.
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@param Timeout Time to wait before abort (in millisecond, ms).
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@retval EFI_SUCCESS The host controller is reset.
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@return Others Failed to reset the host.
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**/
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EFI_STATUS
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EhcResetHC (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Timeout
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);
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/**
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Halt the host controller.
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@param Ehc The EHCI device.
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@param Timeout Time to wait before abort.
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@return EFI_SUCCESS The EHCI is halt.
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@return EFI_TIMEOUT Failed to halt the controller before Timeout.
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**/
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EFI_STATUS
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EhcHaltHC (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Timeout
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);
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/**
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Set the EHCI to run.
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@param Ehc The EHCI device.
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@param Timeout Time to wait before abort.
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@return EFI_SUCCESS The EHCI is running.
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@return Others Failed to set the EHCI to run.
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**/
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EFI_STATUS
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EhcRunHC (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Timeout
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);
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/**
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Initialize the HC hardware.
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EHCI spec lists the five things to do to initialize the hardware:
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1. Program CTRLDSSEGMENT
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2. Set USBINTR to enable interrupts
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3. Set periodic list base
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4. Set USBCMD, interrupt threshold, frame list size etc
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5. Write 1 to CONFIGFLAG to route all ports to EHCI
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@param Ehc The EHCI device.
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@return EFI_SUCCESS The EHCI has come out of halt state.
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@return EFI_TIMEOUT Time out happened.
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**/
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EFI_STATUS
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EhcInitHC (
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IN USB2_HC_DEV *Ehc
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);
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#endif
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