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PCI22/PCI23/PCI30 spec were reviewed and the missing definitions were added to accordingly Pci22.h/Pci23.h/Pci30.h. All other class code definitions that are not defined in PCI Local Bus specification but in PCI Code and ID Assignment specification are defined in PciCodeId.h. Signed-off-by: Ruiyu Ni<ruiyu.ni@intel.com> Reviewed-by: Liming Gao<liming.gao@intel.com> Reviewed-by: Hot Tian<hot.tian@intel.com> Reviewed-by: Elvin Li<elvin.li@intel.com> Reviewed-by: Feng Tian<feng.tian@intel.com> Reviewed-by: Jiewen Yao<jiewen.yao@intel.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13919 6f19259b-4bc3-4df7-8a09-765794883524
101 lines
2.8 KiB
C
101 lines
2.8 KiB
C
/** @file
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The file lists the PCI class codes only defined in PCI code and ID assignment specification
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revision 1.3.
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Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __PCI_CODE_ID_H__
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#define __PCI_CODE_ID_H__
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///
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/// PCI_CLASS_MASS_STORAGE, Base Class 01h.
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///
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///@{
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#define PCI_IF_MASS_STORAGE_SCSI_VENDOR_SPECIFIC 0x00
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#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_PQI 0x11
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#define PCI_IF_MASS_STORAGE_SCSI_CONTROLLER_PQI 0x12
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#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_CONTROLLER_PQI 0x13
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#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_NVM_EXPRESS 0x21
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#define PCI_IF_MASS_STORAGE_SATA_SERIAL_BUS 0x02
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#define PCI_CLASS_MASS_STORAGE_SAS 0x07
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#define PCI_IF_MASS_STORAGE_SAS 0x00
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#define PCI_IF_MASS_STORAGE_SAS_SERIAL_BUS 0x01
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#define PCI_CLASS_MASS_STORAGE_SOLID_STATE 0x08
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#define PCI_IF_MASS_STORAGE_SOLID_STATE 0x00
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#define PCI_IF_MASS_STORAGE_SOLID_STATE_NVMHCI 0x01
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#define PCI_IF_MASS_STORAGE_SOLID_STATE_ENTERPRISE_NVMHCI 0x02
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///@}
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///
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/// PCI_CLASS_NETWORK, Base Class 02h.
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///
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///@{
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#define PCI_CLASS_NETWORK_INFINIBAND 0x07
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///@}
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///
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/// PCI_CLASS_MEDIA, Base Class 04h.
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///
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///@{
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#define PCI_CLASS_MEDIA_MIXED_MODE 0x03
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///@}
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///
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/// PCI_CLASS_BRIDGE, Base Class 06h.
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///
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///@{
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#define PCI_CLASS_BRIDGE_ADVANCED_SWITCHING_TO_PCI 0x0B
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#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_CUSTOM 0x00
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#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_ASI_SIG 0x01
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///@}
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///
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/// PCI_CLASS_SYSTEM_PERIPHERAL, Base Class 08h.
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///
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///@{
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#define PCI_IF_HPET 0x03
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#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05
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#define PCI_SUBCLASS_IOMMU 0x06
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///@}
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///
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/// PCI_CLASS_PROCESSOR, Base Class 0Bh.
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///
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///@{
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#define PCI_SUBCLASS_PROC_OTHER 0x80
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///@}
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///
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/// PCI_CLASS_SERIAL, Base Class 0Ch.
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///
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///@{
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#define PCI_IF_XHCI 0x30
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#define PCI_CLASS_SERIAL_OTHER 0x80
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///@}
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///
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/// PCI_CLASS_SATELLITE, Base Class 0Fh.
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///
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///@{
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#define PCI_SUBCLASS_SATELLITE_OTHER 0x80
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///@}
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///
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/// PCI_CLASS_PROCESSING_ACCELERATOR, Base Class 12h.
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///
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///@{
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#define PCI_CLASS_PROCESSING_ACCELERATOR 0x12
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///@}
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#endif
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