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3402aac7d9
Trailing spaces create issue/warning when generating/applying patches. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
120 lines
3.5 KiB
NASM
120 lines
3.5 KiB
NASM
//------------------------------------------------------------------------------
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//
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// Copyright (c) 2011, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//------------------------------------------------------------------------------
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EXPORT ArmReadCntFrq
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EXPORT ArmWriteCntFrq
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EXPORT ArmReadCntPct
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EXPORT ArmReadCntkCtl
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EXPORT ArmWriteCntkCtl
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EXPORT ArmReadCntpTval
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EXPORT ArmWriteCntpTval
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EXPORT ArmReadCntpCtl
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EXPORT ArmWriteCntpCtl
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EXPORT ArmReadCntvTval
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EXPORT ArmWriteCntvTval
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EXPORT ArmReadCntvCtl
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EXPORT ArmWriteCntvCtl
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EXPORT ArmReadCntvCt
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EXPORT ArmReadCntpCval
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EXPORT ArmWriteCntpCval
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EXPORT ArmReadCntvCval
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EXPORT ArmWriteCntvCval
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EXPORT ArmReadCntvOff
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EXPORT ArmWriteCntvOff
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AREA ArmV7ArchTimerSupport, CODE, READONLY
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PRESERVE8
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ArmReadCntFrq
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mrc p15, 0, r0, c14, c0, 0 ; Read CNTFRQ
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bx lr
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ArmWriteCntFrq
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mcr p15, 0, r0, c14, c0, 0 ; Write to CNTFRQ
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bx lr
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ArmReadCntPct
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mrrc p15, 0, r0, r1, c14 ; Read CNTPT (Physical counter register)
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bx lr
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ArmReadCntkCtl
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mrc p15, 0, r0, c14, c1, 0 ; Read CNTK_CTL (Timer PL1 Control Register)
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bx lr
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ArmWriteCntkCtl
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mcr p15, 0, r0, c14, c1, 0 ; Write to CNTK_CTL (Timer PL1 Control Register)
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bx lr
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ArmReadCntpTval
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mrc p15, 0, r0, c14, c2, 0 ; Read CNTP_TVAL (PL1 physical timer value register)
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bx lr
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ArmWriteCntpTval
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mcr p15, 0, r0, c14, c2, 0 ; Write to CNTP_TVAL (PL1 physical timer value register)
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bx lr
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ArmReadCntpCtl
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mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register)
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bx lr
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ArmWriteCntpCtl
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mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register)
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bx lr
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ArmReadCntvTval
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mrc p15, 0, r0, c14, c3, 0 ; Read CNTV_TVAL (Virtual Timer Value register)
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bx lr
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ArmWriteCntvTval
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mcr p15, 0, r0, c14, c3, 0 ; Write to CNTV_TVAL (Virtual Timer Value register)
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bx lr
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ArmReadCntvCtl
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mrc p15, 0, r0, c14, c3, 1 ; Read CNTV_CTL (Virtual Timer Control Register)
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bx lr
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ArmWriteCntvCtl
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mcr p15, 0, r0, c14, c3, 1 ; Write to CNTV_CTL (Virtual Timer Control Register)
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bx lr
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ArmReadCntvCt
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mrrc p15, 1, r0, r1, c14 ; Read CNTVCT (Virtual Count Register)
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bx lr
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ArmReadCntpCval
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mrrc p15, 2, r0, r1, c14 ; Read CNTP_CTVAL (Physical Timer Compare Value Register)
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bx lr
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ArmWriteCntpCval
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mcrr p15, 2, r0, r1, c14 ; Write to CNTP_CTVAL (Physical Timer Compare Value Register)
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bx lr
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ArmReadCntvCval
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mrrc p15, 3, r0, r1, c14 ; Read CNTV_CTVAL (Virtual Timer Compare Value Register)
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bx lr
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ArmWriteCntvCval
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mcrr p15, 3, r0, r1, c14 ; write to CNTV_CTVAL (Virtual Timer Compare Value Register)
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bx lr
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ArmReadCntvOff
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mrrc p15, 4, r0, r1, c14 ; Read CNTVOFF (virtual Offset register)
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bx lr
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ArmWriteCntvOff
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mcrr p15, 4, r0, r1, c14 ; Write to CNTVOFF (Virtual Offset register)
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bx lr
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END
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