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d8387fa4af
Signed-off-by: jljusten Reviewed-by: mdkinney git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11845 6f19259b-4bc3-4df7-8a09-765794883524
236 lines
6.2 KiB
C
236 lines
6.2 KiB
C
/** @file
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Definition of FDC registers and structures.
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Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions
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of the BSD License which accompanies this distribution. The
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full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _PEI_RECOVERY_FDC_H_
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#define _PEI_RECOVERY_FDC_H_
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//
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// FDC Registers
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//
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#define FDC_REGISTER_DOR 2 //Digital Output Register
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#define FDC_REGISTER_MSR 4 //Main Status Register
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#define FDC_REGISTER_DTR 5 //Data Register
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#define FDC_REGISTER_CCR 7 //Configuration Control Register(data rate select)
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#define FDC_REGISTER_DIR 7 //Digital Input Register(diskchange)
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//
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// FDC Register Bit Definitions
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//
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//
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// Digital Out Register(WO)
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//
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#define SELECT_DRV BIT0 // Select Drive: 0=A 1=B
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#define RESET_FDC BIT2 // Reset FDC
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#define INT_DMA_ENABLE BIT3 // Enable Int & DMA
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#define DRVA_MOTOR_ON BIT4 // Turn On Drive A Motor
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#define DRVB_MOTOR_ON BIT5 // Turn On Drive B Motor
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//
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// Main Status Register(RO)
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//
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#define MSR_DAB BIT0 // Drive A Busy
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#define MSR_DBB BIT1 // Drive B Busy
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#define MSR_CB BIT4 // FDC Busy
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#define MSR_NDM BIT5 // Non-DMA Mode
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#define MSR_DIO BIT6 // Data Input/Output
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#define MSR_RQM BIT7 // Request For Master
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//
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// Configuration Control Register(WO)
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//
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#define CCR_DRC (BIT0 | BIT1) // Data Rate select
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//
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// Digital Input Register(RO)
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//
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#define DIR_DCL BIT7 // Disk change line
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#define DRC_500KBS 0x0 // 500K
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#define DRC_300KBS 0x01 // 300K
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#define DRC_250KBS 0x02 // 250K
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//
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// FDC Command Code
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//
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#define READ_DATA_CMD 0x06
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#define SEEK_CMD 0x0F
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#define RECALIBRATE_CMD 0x07
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#define SENSE_INT_STATUS_CMD 0x08
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#define SPECIFY_CMD 0x03
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#define SENSE_DRV_STATUS_CMD 0x04
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///
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/// CMD_MT: Multi_Track Selector
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/// when set , this flag selects the multi-track operating mode.
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/// In this mode, the FDC treats a complete cylinder under head0 and 1 as a single track
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///
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#define CMD_MT BIT7
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///
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/// CMD_MFM: MFM/FM Mode Selector
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/// A one selects the double density(MFM) mode
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/// A zero selects single density (FM) mode
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///
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#define CMD_MFM BIT6
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///
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/// CMD_SK: Skip Flag
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/// When set to 1, sectors containing a deleted data address mark will automatically be skipped
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/// during the execution of Read Data.
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/// When set to 0, the sector is read or written the same as the read and write commands.
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///
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#define CMD_SK BIT5
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//
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// FDC Status Register Bit Definitions
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//
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//
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// Status Register 0
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//
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#define STS0_IC (BIT7 | BIT6) // Interrupt Code
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#define STS0_SE BIT5 // Seek End: the FDC completed a seek or recalibrate command
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#define STS0_EC BIT4 // Equipment Check
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#define STS0_NR BIT3 // Not Ready(unused), this bit is always 0
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#define STS0_HA BIT2 // Head Address: the current head address
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//
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// STS0_US1 & STS0_US0: Drive Select(the current selected drive)
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//
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#define STS0_US1 BIT1 // Unit Select1
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#define STS0_US0 BIT0 // Unit Select0
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//
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// Status Register 1
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//
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#define STS1_EN BIT7 // End of Cylinder
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//
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// BIT6 is unused
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//
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#define STS1_DE BIT5 // Data Error: The FDC detected a CRC error in either the ID field or data field of a sector
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#define STS1_OR BIT4 // Overrun/Underrun: Becomes set if FDC does not receive CPU or DMA service within the required time interval
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//
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// BIT3 is unused
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//
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#define STS1_ND BIT2 // No data
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#define STS1_NW BIT1 // Not Writable
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#define STS1_MA BIT0 // Missing Address Mark
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//
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// Status Register 2
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//
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// BIT7 is unused
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//
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#define STS2_CM BIT6 // Control Mark
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#define STS2_DD BIT5 // Data Error in Data Field: The FDC detected a CRC error in the data field
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#define STS2_WC BIT4 // Wrong Cylinder: The track address from sector ID field is different from the track address maintained inside FDC
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//
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// BIT3 is unused
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// BIT2 is unused
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//
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#define STS2_BC BIT1 // Bad Cylinder
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#define STS2_MD BIT0 // Missing Address Mark in DataField
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//
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// Status Register 3
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//
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// BIT7 is unused
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//
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#define STS3_WP BIT6 // Write Protected
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//
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// BIT5 is unused
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//
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#define STS3_T0 BIT4 // Track 0
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//
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// BIT3 is unused
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//
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#define STS3_HD BIT2 // Head Address
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//
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// STS3_US1 & STS3_US0 : Drive Select
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//
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#define STS3_US1 BIT1 // Unit Select1
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#define STS3_US0 BIT0 // Unit Select0
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//
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// Status Register 0 Interrupt Code Description
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//
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#define IC_NT 0x0 // Normal Termination of Command
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#define IC_AT 0x40 // Abnormal Termination of Command
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#define IC_IC 0x80 // Invalid Command
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#define IC_ATRC 0xC0 // Abnormal Termination caused by Polling
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///
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/// Table of parameters for diskette
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///
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typedef struct {
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UINT8 EndOfTrack; ///< End of track
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UINT8 GapLength; ///< Gap length
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UINT8 DataLength; ///< Data length
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UINT8 Number; ///< Number of bytes per sector
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UINT8 MaxTrackNum;
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UINT8 MotorStartTime;
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UINT8 MotorOffTime;
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UINT8 HeadSettlingTime;
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UINT8 DataTransferRate;
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} DISKET_PARA_TABLE;
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///
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/// Structure for FDC Command Packet 1
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///
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typedef struct {
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UINT8 CommandCode;
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UINT8 DiskHeadSel;
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UINT8 Cylinder;
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UINT8 Head;
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UINT8 Sector;
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UINT8 Number;
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UINT8 EndOfTrack;
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UINT8 GapLength;
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UINT8 DataLength;
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} FDC_COMMAND_PACKET1;
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///
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/// Structure for FDC Command Packet 2
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///
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typedef struct {
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UINT8 CommandCode;
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UINT8 DiskHeadSel;
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} FDC_COMMAND_PACKET2;
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///
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/// Structure for FDC Specify Command
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///
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typedef struct {
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UINT8 CommandCode;
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UINT8 SrtHut;
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UINT8 HltNd;
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} FDC_SPECIFY_CMD;
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///
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/// Structure for FDC Seek Command
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///
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typedef struct {
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UINT8 CommandCode;
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UINT8 DiskHeadSel;
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UINT8 NewCylinder;
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} FDC_SEEK_CMD;
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///
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/// Structure for FDC Result Packet
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///
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typedef struct {
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UINT8 Status0;
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UINT8 Status1;
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UINT8 Status2;
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UINT8 CylinderNumber;
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UINT8 HeaderAddress;
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UINT8 Record;
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UINT8 Number;
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} FDC_RESULT_PACKET;
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#endif
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