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The VA address space has a maximum address width of 48 bits in AArch64 state; 48 bits address width limit will provide better compatibility than 40 bits for future CPU. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Olivier Martin <Olivier.Martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17526 6f19259b-4bc3-4df7-8a09-765794883524 |
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| .. | ||
| Chipset | ||
| Guid | ||
| IndustryStandard | ||
| Library | ||
| Ppi | ||
| Protocol | ||
| AsmMacroIoLib.h | ||
| AsmMacroIoLib.inc | ||
| AsmMacroIoLibV8.h | ||