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https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
261 lines
8.5 KiB
C
261 lines
8.5 KiB
C
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/*++
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Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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vlvAccess.h
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Abstract:
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Macros to simplify and abstract the interface to PCI configuration.
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--*/
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#ifndef _VLVACCESS_H_INCLUDED_
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#define _VLVACCESS_H_INCLUDED_
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#include "Valleyview.h"
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#include "VlvCommonDefinitions.h"
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#include <Library/IoLib.h>
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//
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// Memory Mapped IO access macros used by MSG BUS LIBRARY
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//
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#define MmioAddress( BaseAddr, Register ) \
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( (UINTN)BaseAddr + \
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(UINTN)(Register) \
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)
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//
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// UINT32
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//
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#define Mmio32Ptr( BaseAddr, Register ) \
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( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) )
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#define Mmio32( BaseAddr, Register ) \
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*Mmio32Ptr( BaseAddr, Register )
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#define Mmio32Or( BaseAddr, Register, OrData ) \
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Mmio32( BaseAddr, Register ) = \
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(UINT32) ( \
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Mmio32( BaseAddr, Register ) | \
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(UINT32)(OrData) \
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)
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#define Mmio32And( BaseAddr, Register, AndData ) \
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Mmio32( BaseAddr, Register ) = \
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(UINT32) ( \
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Mmio32( BaseAddr, Register ) & \
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(UINT32)(AndData) \
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)
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#define Mmio32AndThenOr( BaseAddr, Register, AndData, OrData ) \
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Mmio32( BaseAddr, Register ) = \
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(UINT32) ( \
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( Mmio32( BaseAddr, Register ) & \
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(UINT32)(AndData) \
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) | \
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(UINT32)(OrData) \
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)
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//
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// UINT16
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//
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#define Mmio16Ptr( BaseAddr, Register ) \
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( (volatile UINT16 *)MmioAddress( BaseAddr, Register ) )
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#define Mmio16( BaseAddr, Register ) \
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*Mmio16Ptr( BaseAddr, Register )
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#define Mmio16Or( BaseAddr, Register, OrData ) \
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Mmio16( BaseAddr, Register ) = \
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(UINT16) ( \
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Mmio16( BaseAddr, Register ) | \
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(UINT16)(OrData) \
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)
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#define Mmio16And( BaseAddr, Register, AndData ) \
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Mmio16( BaseAddr, Register ) = \
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(UINT16) ( \
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Mmio16( BaseAddr, Register ) & \
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(UINT16)(AndData) \
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)
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#define Mmio16AndThenOr( BaseAddr, Register, AndData, OrData ) \
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Mmio16( BaseAddr, Register ) = \
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(UINT16) ( \
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( Mmio16( BaseAddr, Register ) & \
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(UINT16)(AndData) \
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) | \
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(UINT16)(OrData) \
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)
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//
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// UINT8
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//
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#define Mmio8Ptr( BaseAddr, Register ) \
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( (volatile UINT8 *)MmioAddress( BaseAddr, Register ) )
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#define Mmio8( BaseAddr, Register ) \
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*Mmio8Ptr( BaseAddr, Register )
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#define Mmio8Or( BaseAddr, Register, OrData ) \
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Mmio8( BaseAddr, Register ) = \
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(UINT8) ( \
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Mmio8( BaseAddr, Register ) | \
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(UINT8)(OrData) \
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)
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#define Mmio8And( BaseAddr, Register, AndData ) \
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Mmio8( BaseAddr, Register ) = \
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(UINT8) ( \
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Mmio8( BaseAddr, Register ) & \
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(UINT8)(AndData) \
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)
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#define Mmio8AndThenOr( BaseAddr, Register, AndData, OrData ) \
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Mmio8( BaseAddr, Register ) = \
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(UINT8) ( \
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( Mmio8( BaseAddr, Register ) & \
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(UINT8)(AndData) \
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) | \
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(UINT8)(OrData) \
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)
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//
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// MSG BUS API
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//
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#define MSG_BUS_ENABLED 0x000000F0
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#define MSGBUS_MASKHI 0xFFFFFF00
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#define MSGBUS_MASKLO 0x000000FF
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#define MESSAGE_BYTE_EN BIT4
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#define MESSAGE_WORD_EN BIT4 | BIT5
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#define MESSAGE_DWORD_EN BIT4 | BIT5 | BIT6 | BIT7
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#define SIDEBAND_OPCODE 0x78
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#define MEMREAD_OPCODE 0x00000000
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#define MEMWRITE_OPCODE 0x01000000
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/***************************/
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//
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// Memory mapped PCI IO
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//
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#define PciCfgPtr(Bus, Device, Function, Register )\
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(UINTN)(Bus << 20) + \
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(UINTN)(Device << 15) + \
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(UINTN)(Function << 12) + \
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(UINTN)(Register)
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#define PciCfg32Read_CF8CFC(B,D,F,R) \
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(UINT32)(IoOut32(0xCF8,(0x80000000|(B<<16)|(D<<11)|(F<<8)|(R))),IoIn32(0xCFC))
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#define PciCfg32Write_CF8CFC(B,D,F,R,Data) \
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(IoOut32(0xCF8,(0x80000000|(B<<16)|(D<<11)|(F<<8)|(R))),IoOut32(0xCFC,Data))
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#define PciCfg32Or_CF8CFC(B,D,F,R,O) \
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PciCfg32Write_CF8CFC(B,D,F,R, \
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(PciCfg32Read_CF8CFC(B,D,F,R) | (O)))
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#define PciCfg32And_CF8CFC(B,D,F,R,A) \
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PciCfg32Write_CF8CFC(B,D,F,R, \
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(PciCfg32Read_CF8CFC(B,D,F,R) & (A)))
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#define PciCfg32AndThenOr_CF8CFC(B,D,F,R,A,O) \
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PciCfg32Write_CF8CFC(B,D,F,R, \
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(PciCfg32Read_CF8CFC(B,D,F,R) & (A)) | (O))
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//
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// Device 0, Function 0
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//
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#define McD0PciCfg64(Register) MmPci64 (0, MC_BUS, 0, 0, Register)
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#define McD0PciCfg64Or(Register, OrData) MmPci64Or (0, MC_BUS, 0, 0, Register, OrData)
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#define McD0PciCfg64And(Register, AndData) MmPci64And (0, MC_BUS, 0, 0, Register, AndData)
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#define McD0PciCfg64AndThenOr(Register, AndData, OrData) MmPci64AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
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#define McD0PciCfg32(Register) MmPci32 (0, MC_BUS, 0, 0, Register)
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#define McD0PciCfg32Or(Register, OrData) MmPci32Or (0, MC_BUS, 0, 0, Register, OrData)
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#define McD0PciCfg32And(Register, AndData) MmPci32And (0, MC_BUS, 0, 0, Register, AndData)
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#define McD0PciCfg32AndThenOr(Register, AndData, OrData) MmPci32AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
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#define McD0PciCfg16(Register) MmPci16 (0, MC_BUS, 0, 0, Register)
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#define McD0PciCfg16Or(Register, OrData) MmPci16Or (0, MC_BUS, 0, 0, Register, OrData)
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#define McD0PciCfg16And(Register, AndData) MmPci16And (0, MC_BUS, 0, 0, Register, AndData)
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#define McD0PciCfg16AndThenOr(Register, AndData, OrData) MmPci16AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
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#define McD0PciCfg8(Register) MmPci8 (0, MC_BUS, 0, 0, Register)
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#define McD0PciCfg8Or(Register, OrData) MmPci8Or (0, MC_BUS, 0, 0, Register, OrData)
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#define McD0PciCfg8And(Register, AndData) MmPci8And (0, MC_BUS, 0, 0, Register, AndData)
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#define McD0PciCfg8AndThenOr( Register, AndData, OrData ) MmPci8AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
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//
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// Device 2, Function 0
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//
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#define McD2PciCfg64(Register) MmPci64 (0, MC_BUS, 2, 0, Register)
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#define McD2PciCfg64Or(Register, OrData) MmPci64Or (0, MC_BUS, 2, 0, Register, OrData)
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#define McD2PciCfg64And(Register, AndData) MmPci64And (0, MC_BUS, 2, 0, Register, AndData)
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#define McD2PciCfg64AndThenOr(Register, AndData, OrData) MmPci64AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData)
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#define McD2PciCfg32(Register) MmPci32 (0, MC_BUS, 2, 0, Register)
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#define McD2PciCfg32Or(Register, OrData) MmPci32Or (0, MC_BUS, 2, 0, Register, OrData)
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#define McD2PciCfg32And(Register, AndData) MmPci32And (0, MC_BUS, 2, 0, Register, AndData)
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#define McD2PciCfg32AndThenOr(Register, AndData, OrData) MmPci32AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData)
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#define McD2PciCfg16(Register) MmPci16 (0, MC_BUS, 2, 0, Register)
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#define McD2PciCfg16Or(Register, OrData) MmPci16Or (0, MC_BUS, 2, 0, Register, OrData)
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#define McD2PciCfg16And(Register, AndData) MmPci16And (0, MC_BUS, 2, 0, Register, AndData)
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#define McD2PciCfg16AndThenOr(Register, AndData, OrData) MmPci16AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData)
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#define McD2PciCfg8(Register) MmPci8 (0, MC_BUS, 2, 0, Register)
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#define McD2PciCfg8Or(Register, OrData) MmPci8Or (0, MC_BUS, 2, 0, Register, OrData)
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#define McD2PciCfg8And(Register, AndData) MmPci8And (0, MC_BUS, 2, 0, Register, AndData)
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//
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// IO
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//
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#ifndef IoIn8
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#define IoIn8(Port) \
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IoRead8(Port)
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#define IoIn16(Port) \
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IoRead16(Port)
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#define IoIn32(Port) \
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IoRead32(Port)
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#define IoOut8(Port, Data) \
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IoWrite8(Port, Data)
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#define IoOut16(Port, Data) \
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IoWrite16(Port, Data)
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#define IoOut32(Port, Data) \
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IoWrite32(Port, Data)
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#endif
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#endif
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