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7ede80607b
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Qian Yi <yi.qian@intel.com> Reviewed-by: Zailing Sun <zailiang.sun@intel.com>
91 lines
3.1 KiB
Plaintext
91 lines
3.1 KiB
Plaintext
/**************************************************************************;
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;* *;
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;* *;
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;* Intel Corporation - ACPI Reference Code for the Baytrail *;
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;* Family of Customer Reference Boards. *;
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;* *;
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;* *;
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;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;
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;
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;* *;
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;* *;
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;**************************************************************************/
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Scope (\_SB.PCI0)
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{
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Device(PDRC) // PCI Device Resource Consumption
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{
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Name(_HID,EISAID("PNP0C02"))
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Name(_UID,1)
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Name(BUF0,ResourceTemplate()
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{
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//
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// PCI Express BAR _BAS and _LEN will be updated in _CRS below according to B0:D0:F0:Reg.60h
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// Forced hard code at the moment.
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//
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//Memory32Fixed(ReadWrite,0,0,PCIX) // PCIEX BAR
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Memory32Fixed(ReadWrite,0x0E0000000,0x010000000,PCIX)
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//
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// SPI BAR. Check if the hard code meets the real configuration.
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// If not, dynamically update it like the _CRS method below.
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//
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Memory32Fixed(ReadWrite,0x0FED01000,0x01000,SPIB) // SPI BAR
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//
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// PMC BAR. Check if the hard code meets the real configuration.
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// If not, dynamically update it like the _CRS method below.
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//
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Memory32Fixed(ReadWrite,0x0FED03000,0x01000,PMCB) // PMC BAR
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//
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// SMB BAR. Check if the hard code meets the real configuration.
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// If not, dynamically update it like the _CRS method below.
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//
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Memory32Fixed(ReadWrite,0x0FED04000,0x01000,SMBB) // SMB BAR
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//
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// IO BAR. Check if the hard code meets the real configuration.
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// If not, dynamically update it like the _CRS method below.
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//
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Memory32Fixed(ReadWrite,0x0FED0C000,0x04000,IOBR) // IO BAR
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//
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// ILB BAR. Check if the hard code meets the real configuration.
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// If not, dynamically update it like the _CRS method below.
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//
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Memory32Fixed(ReadWrite,0x0FED08000,0x01000,ILBB) // ILB BAR
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//
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// RCRB BAR _BAS will be updated in _CRS below according to B0:D31:F0:Reg.F0h
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//
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Memory32Fixed(ReadWrite,0x0FED1C000,0x01000,RCRB) // RCRB BAR
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//
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// Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF)
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//
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Memory32Fixed (ReadOnly, 0x0FEE00000, 0x0100000, LIOH)
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//
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// MPHY BAR. Check if the hard code meets the real configuration.
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// If not, dynamically update it like the _CRS method below.
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//
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Memory32Fixed(ReadWrite,0x0FEF00000,0x0100000,MPHB) // MPHY BAR
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})
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Method(_CRS,0,Serialized)
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{
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Return(BUF0)
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}
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}
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}
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