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7ede80607b
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Qian Yi <yi.qian@intel.com> Reviewed-by: Zailing Sun <zailiang.sun@intel.com>
50 lines
2.1 KiB
Plaintext
50 lines
2.1 KiB
Plaintext
/**************************************************************************;
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;* *;
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;* *;
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;* Intel Corporation - ACPI Reference Code for the Baytrail *;
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;* Family of Customer Reference Boards. *;
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;* *;
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;* *;
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;* Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved *;
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;
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;* *;
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;* *;
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;**************************************************************************/
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// NOTE: The _PDC Implementation is out of the scope of this
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// reference code. Please see the latest Hyper-Threading Technology
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// Reference Code for complete implementation details.
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Scope(\_PR)
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{
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Processor(CPU0, // Unique name for Processor 0.
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1, // Unique ID for Processor 0.
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0x00, // CPU0 ACPI P_BLK address = ACPIBASE + 10h.
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0) // CPU0 P_BLK length = 6 bytes.
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{}
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Processor(CPU1, // Unique name for Processor 1.
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2, // Unique ID for Processor 1.
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0x00,
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0) // CPU1 P_BLK length = 6 bytes.
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{}
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Processor(CPU2, // Unique name for Processor 2.
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3, // Unique ID for Processor 2.
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0x00,
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0) // CPU2 P_BLK length = 6 bytes.
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{}
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Processor(CPU3, // Unique name for Processor 3.
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4, // Unique ID for Processor 3.
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0x00,
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0) // CPU3 P_BLK length = 6 bytes.
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{}
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} // End _PR
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