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ArmInvalidateInstructionAndDataTlb() was doing the same thing as ArmInvalidateTlb(). Both invalidate Data and Instruction TLBs. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16253 6f19259b-4bc3-4df7-8a09-765794883524 |
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| .. | ||
| ArmArchTimer.h | ||
| ArmCpuLib.h | ||
| ArmDisassemblerLib.h | ||
| ArmGenericTimerCounterLib.h | ||
| ArmGicLib.h | ||
| ArmHvcLib.h | ||
| ArmLib.h | ||
| ArmSmcLib.h | ||
| BdsLib.h | ||
| DefaultExceptionHandlerLib.h | ||
| SemihostLib.h | ||
| UncachedMemoryAllocationLib.h | ||