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cd68e4a8de
Add stride PCD to MdeModulePkg to support 16550 UARTs with a register stride that is not 1 byte. The default value is 1 byte. Quark SoC uses a stride of 4 bytes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17215 6f19259b-4bc3-4df7-8a09-765794883524
764 lines
24 KiB
C
764 lines
24 KiB
C
/** @file
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16550 UART Serial Port library functions
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(C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>
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Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Base.h>
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#include <IndustryStandard/Pci.h>
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#include <Library/SerialPortLib.h>
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#include <Library/PcdLib.h>
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#include <Library/IoLib.h>
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#include <Library/PciLib.h>
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#include <Library/PlatformHookLib.h>
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#include <Library/BaseLib.h>
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//
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// PCI Defintions.
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//
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#define PCI_BRIDGE_32_BIT_IO_SPACE 0x01
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//
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// 16550 UART register offsets and bitfields
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//
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#define R_UART_RXBUF 0
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#define R_UART_TXBUF 0
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#define R_UART_BAUD_LOW 0
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#define R_UART_BAUD_HIGH 1
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#define R_UART_FCR 2
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#define B_UART_FCR_FIFOE BIT0
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#define B_UART_FCR_FIFO64 BIT5
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#define R_UART_LCR 3
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#define B_UART_LCR_DLAB BIT7
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#define R_UART_MCR 4
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#define B_UART_MCR_RTS BIT1
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#define R_UART_LSR 5
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#define B_UART_LSR_RXRDY BIT0
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#define B_UART_LSR_TXRDY BIT5
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#define B_UART_LSR_TEMT BIT6
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#define R_UART_MSR 6
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#define B_UART_MSR_CTS BIT4
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#define B_UART_MSR_DSR BIT5
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//
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// 4-byte structure for each PCI node in PcdSerialPciDeviceInfo
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//
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typedef struct {
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UINT8 Device;
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UINT8 Function;
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UINT16 PowerManagementStatusAndControlRegister;
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} PCI_UART_DEVICE_INFO;
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/**
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Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is read from
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MMIO space. If PcdSerialUseMmio is FALSE, then the value is read from I/O space. The
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parameter Offset is added to the base address of the 16550 registers that is specified
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by PcdSerialRegisterBase.
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@param Base The base address register of UART device.
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@param Offset The offset of the 16550 register to read.
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@return The value read from the 16550 register.
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**/
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UINT8
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SerialPortReadRegister (
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UINTN Base,
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UINTN Offset
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)
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{
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if (PcdGetBool (PcdSerialUseMmio)) {
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return MmioRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
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} else {
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return IoRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
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}
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}
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/**
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Write an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is written to
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MMIO space. If PcdSerialUseMmio is FALSE, then the value is written to I/O space. The
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parameter Offset is added to the base address of the 16550 registers that is specified
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by PcdSerialRegisterBase.
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@param Base The base address register of UART device.
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@param Offset The offset of the 16550 register to write.
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@param Value The value to write to the 16550 register specified by Offset.
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@return The value written to the 16550 register.
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**/
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UINT8
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SerialPortWriteRegister (
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UINTN Base,
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UINTN Offset,
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UINT8 Value
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)
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{
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if (PcdGetBool (PcdSerialUseMmio)) {
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return MmioWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), Value);
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} else {
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return IoWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), Value);
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}
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}
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/**
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Update the value of an 16-bit PCI configuration register in a PCI device. If the
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PCI Configuration register specified by PciAddress is already programmed with a
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non-zero value, then return the current value. Otherwise update the PCI configuration
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register specified by PciAddress with the value specified by Value and return the
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value programmed into the PCI configuration register. All values must be masked
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using the bitmask specified by Mask.
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@param PciAddress PCI Library address of the PCI Configuration register to update.
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@param Value The value to program into the PCI Configuration Register.
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@param Mask Bitmask of the bits to check and update in the PCI configuration register.
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**/
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UINT16
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SerialPortLibUpdatePciRegister16 (
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UINTN PciAddress,
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UINT16 Value,
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UINT16 Mask
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)
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{
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UINT16 CurrentValue;
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CurrentValue = PciRead16 (PciAddress) & Mask;
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if (CurrentValue != 0) {
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return CurrentValue;
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}
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return PciWrite16 (PciAddress, Value & Mask);
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}
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/**
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Update the value of an 32-bit PCI configuration register in a PCI device. If the
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PCI Configuration register specified by PciAddress is already programmed with a
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non-zero value, then return the current value. Otherwise update the PCI configuration
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register specified by PciAddress with the value specified by Value and return the
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value programmed into the PCI configuration register. All values must be masked
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using the bitmask specified by Mask.
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@param PciAddress PCI Library address of the PCI Configuration register to update.
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@param Value The value to program into the PCI Configuration Register.
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@param Mask Bitmask of the bits to check and update in the PCI configuration register.
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@return The Secondary bus number that is actually programed into the PCI to PCI Bridge device.
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**/
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UINT32
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SerialPortLibUpdatePciRegister32 (
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UINTN PciAddress,
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UINT32 Value,
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UINT32 Mask
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)
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{
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UINT32 CurrentValue;
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CurrentValue = PciRead32 (PciAddress) & Mask;
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if (CurrentValue != 0) {
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return CurrentValue;
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}
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return PciWrite32 (PciAddress, Value & Mask);
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}
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/**
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Retrieve the I/O or MMIO base address register for the PCI UART device.
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This function assumes Root Bus Numer is Zero, and enables I/O and MMIO in PCI UART
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Device if they are not already enabled.
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@return The base address register of the UART device.
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**/
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UINTN
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GetSerialRegisterBase (
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VOID
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)
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{
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UINTN PciLibAddress;
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UINTN BusNumber;
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UINTN SubordinateBusNumber;
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UINT32 ParentIoBase;
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UINT32 ParentIoLimit;
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UINT16 ParentMemoryBase;
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UINT16 ParentMemoryLimit;
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UINT32 IoBase;
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UINT32 IoLimit;
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UINT16 MemoryBase;
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UINT16 MemoryLimit;
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UINTN SerialRegisterBase;
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UINTN BarIndex;
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UINT32 RegisterBaseMask;
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PCI_UART_DEVICE_INFO *DeviceInfo;
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//
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// Get PCI Device Info
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//
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DeviceInfo = (PCI_UART_DEVICE_INFO *) PcdGetPtr (PcdSerialPciDeviceInfo);
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//
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// If PCI Device Info is empty, then assume fixed address UART and return PcdSerialRegisterBase
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//
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if (DeviceInfo->Device == 0xff) {
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return (UINTN)PcdGet64 (PcdSerialRegisterBase);
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}
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//
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// Assume PCI Bus 0 I/O window is 0-64KB and MMIO windows is 0-4GB
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//
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ParentMemoryBase = 0 >> 16;
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ParentMemoryLimit = 0xfff00000 >> 16;
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ParentIoBase = 0 >> 12;
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ParentIoLimit = 0xf000 >> 12;
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//
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// Enable I/O and MMIO in PCI Bridge
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// Assume Root Bus Numer is Zero.
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//
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for (BusNumber = 0; (DeviceInfo + 1)->Device != 0xff; DeviceInfo++) {
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//
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// Compute PCI Lib Address to PCI to PCI Bridge
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//
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PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0);
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//
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// Retrieve and verify the bus numbers in the PCI to PCI Bridge
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//
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BusNumber = PciRead8 (PciLibAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
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SubordinateBusNumber = PciRead8 (PciLibAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
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if (BusNumber == 0 || BusNumber > SubordinateBusNumber) {
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return 0;
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}
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//
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// Retrieve and verify the I/O or MMIO decode window in the PCI to PCI Bridge
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//
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if (PcdGetBool (PcdSerialUseMmio)) {
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MemoryLimit = PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit)) & 0xfff0;
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MemoryBase = PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase)) & 0xfff0;
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//
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// If PCI Bridge MMIO window is disabled, then return 0
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//
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if (MemoryLimit < MemoryBase) {
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return 0;
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}
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//
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// If PCI Bridge MMIO window is not in the address range decoded by the parent PCI Bridge, then return 0
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//
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if (MemoryBase < ParentMemoryBase || MemoryBase > ParentMemoryLimit || MemoryLimit > ParentMemoryLimit) {
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return 0;
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}
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ParentMemoryBase = MemoryBase;
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ParentMemoryLimit = MemoryLimit;
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} else {
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IoLimit = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoLimit));
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if ((IoLimit & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {
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IoLimit = IoLimit >> 4;
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} else {
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IoLimit = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoLimitUpper16)) << 4) | (IoLimit >> 4);
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}
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IoBase = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBase));
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if ((IoBase & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {
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IoBase = IoBase >> 4;
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} else {
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IoBase = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBaseUpper16)) << 4) | (IoBase >> 4);
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}
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//
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// If PCI Bridge I/O window is disabled, then return 0
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//
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if (IoLimit < IoBase) {
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return 0;
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}
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//
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// If PCI Bridge I/O window is not in the address range decoded by the parent PCI Bridge, then return 0
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//
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if (IoBase < ParentIoBase || IoBase > ParentIoLimit || IoLimit > ParentIoLimit) {
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return 0;
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}
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ParentIoBase = IoBase;
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ParentIoLimit = IoLimit;
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}
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}
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//
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// Compute PCI Lib Address to PCI UART
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//
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PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0);
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//
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// Find the first IO or MMIO BAR
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//
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RegisterBaseMask = 0xFFFFFFF0;
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for (BarIndex = 0; BarIndex < PCI_MAX_BAR; BarIndex ++) {
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SerialRegisterBase = PciRead32 (PciLibAddress + PCI_BASE_ADDRESSREG_OFFSET + BarIndex * 4);
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if (PcdGetBool (PcdSerialUseMmio) && ((SerialRegisterBase & BIT0) == 0)) {
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//
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// MMIO BAR is found
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//
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RegisterBaseMask = 0xFFFFFFF0;
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break;
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}
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if ((!PcdGetBool (PcdSerialUseMmio)) && ((SerialRegisterBase & BIT0) != 0)) {
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//
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// IO BAR is found
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//
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RegisterBaseMask = 0xFFFFFFF8;
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break;
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}
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}
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//
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// MMIO or IO BAR is not found.
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//
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if (BarIndex == PCI_MAX_BAR) {
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return 0;
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}
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//
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// Program UART BAR
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//
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SerialRegisterBase = SerialPortLibUpdatePciRegister32 (
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PciLibAddress + PCI_BASE_ADDRESSREG_OFFSET + BarIndex * 4,
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(UINT32)PcdGet64 (PcdSerialRegisterBase),
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RegisterBaseMask
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);
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//
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// Verify that the UART BAR is in the address range decoded by the parent PCI Bridge
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//
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if (PcdGetBool (PcdSerialUseMmio)) {
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if (((SerialRegisterBase >> 16) & 0xfff0) < ParentMemoryBase || ((SerialRegisterBase >> 16) & 0xfff0) > ParentMemoryLimit) {
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return 0;
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}
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} else {
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if ((SerialRegisterBase >> 12) < ParentIoBase || (SerialRegisterBase >> 12) > ParentIoLimit) {
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return 0;
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}
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}
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//
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// Enable I/O and MMIO in PCI UART Device if they are not already enabled
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//
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PciOr16 (
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PciLibAddress + PCI_COMMAND_OFFSET,
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PcdGetBool (PcdSerialUseMmio) ? EFI_PCI_COMMAND_MEMORY_SPACE : EFI_PCI_COMMAND_IO_SPACE
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);
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//
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// Force D0 state if a Power Management and Status Register is specified
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//
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if (DeviceInfo->PowerManagementStatusAndControlRegister != 0x00) {
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if ((PciRead16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister) & (BIT0 | BIT1)) != 0x00) {
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PciAnd16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister, (UINT16)~(BIT0 | BIT1));
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//
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// If PCI UART was not in D0, then make sure FIFOs are enabled, but do not reset FIFOs
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//
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SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));
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}
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}
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//
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// Get PCI Device Info
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//
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DeviceInfo = (PCI_UART_DEVICE_INFO *) PcdGetPtr (PcdSerialPciDeviceInfo);
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//
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// Enable I/O or MMIO in PCI Bridge
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// Assume Root Bus Numer is Zero.
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//
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for (BusNumber = 0; (DeviceInfo + 1)->Device != 0xff; DeviceInfo++) {
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//
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// Compute PCI Lib Address to PCI to PCI Bridge
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//
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PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0);
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//
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// Enable the I/O or MMIO decode windows in the PCI to PCI Bridge
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//
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PciOr16 (
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PciLibAddress + PCI_COMMAND_OFFSET,
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PcdGetBool (PcdSerialUseMmio) ? EFI_PCI_COMMAND_MEMORY_SPACE : EFI_PCI_COMMAND_IO_SPACE
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);
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//
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// Force D0 state if a Power Management and Status Register is specified
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//
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if (DeviceInfo->PowerManagementStatusAndControlRegister != 0x00) {
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if ((PciRead16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister) & (BIT0 | BIT1)) != 0x00) {
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PciAnd16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister, (UINT16)~(BIT0 | BIT1));
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}
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}
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BusNumber = PciRead8 (PciLibAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
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}
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return SerialRegisterBase;
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}
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/**
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Return whether the hardware flow control signal allows writing.
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@param SerialRegisterBase The base address register of UART device.
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@retval TRUE The serial port is writable.
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@retval FALSE The serial port is not writable.
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**/
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BOOLEAN
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SerialPortWritable (
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UINTN SerialRegisterBase
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)
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{
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if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
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if (PcdGetBool (PcdSerialDetectCable)) {
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//
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// Wait for both DSR and CTS to be set
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// DSR is set if a cable is connected.
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// CTS is set if it is ok to transmit data
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//
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// DSR CTS Description Action
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// === === ======================================== ========
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// 0 0 No cable connected. Wait
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// 0 1 No cable connected. Wait
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// 1 0 Cable connected, but not clear to send. Wait
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// 1 1 Cable connected, and clear to send. Transmit
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//
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return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase, R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) == (B_UART_MSR_DSR | B_UART_MSR_CTS));
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} else {
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//
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// Wait for both DSR and CTS to be set OR for DSR to be clear.
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// DSR is set if a cable is connected.
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// CTS is set if it is ok to transmit data
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//
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// DSR CTS Description Action
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// === === ======================================== ========
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// 0 0 No cable connected. Transmit
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// 0 1 No cable connected. Transmit
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// 1 0 Cable connected, but not clear to send. Wait
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// 1 1 Cable connected, and clar to send. Transmit
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//
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return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase, R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) != (B_UART_MSR_DSR));
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}
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}
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return TRUE;
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}
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/**
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Initialize the serial device hardware.
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If no initialization is required, then return RETURN_SUCCESS.
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If the serial device was successfully initialized, then return RETURN_SUCCESS.
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If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
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@retval RETURN_SUCCESS The serial device was initialized.
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@retval RETURN_DEVICE_ERROR The serial device could not be initialized.
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**/
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RETURN_STATUS
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EFIAPI
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SerialPortInitialize (
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VOID
|
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)
|
|
{
|
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RETURN_STATUS Status;
|
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UINTN SerialRegisterBase;
|
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UINT32 Divisor;
|
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UINT32 CurrentDivisor;
|
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BOOLEAN Initialized;
|
|
|
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//
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// Perform platform specific initialization required to enable use of the 16550 device
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// at the location specified by PcdSerialUseMmio and PcdSerialRegisterBase.
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//
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Status = PlatformHookSerialPortInitialize ();
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if (RETURN_ERROR (Status)) {
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return Status;
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}
|
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|
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//
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|
// Calculate divisor for baud generator
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|
// Ref_Clk_Rate / Baud_Rate / 16
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//
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|
Divisor = PcdGet32 (PcdSerialClockRate) / (PcdGet32 (PcdSerialBaudRate) * 16);
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if ((PcdGet32 (PcdSerialClockRate) % (PcdGet32 (PcdSerialBaudRate) * 16)) >= PcdGet32 (PcdSerialBaudRate) * 8) {
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Divisor++;
|
|
}
|
|
|
|
//
|
|
// Get the base address of the serial port in either I/O or MMIO space
|
|
//
|
|
SerialRegisterBase = GetSerialRegisterBase ();
|
|
if (SerialRegisterBase ==0) {
|
|
return RETURN_DEVICE_ERROR;
|
|
}
|
|
|
|
//
|
|
// See if the serial port is already initialized
|
|
//
|
|
Initialized = TRUE;
|
|
if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & 0x3F) != (PcdGet8 (PcdSerialLineControl) & 0x3F)) {
|
|
Initialized = FALSE;
|
|
}
|
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) | B_UART_LCR_DLAB));
|
|
CurrentDivisor = SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_HIGH) << 8;
|
|
CurrentDivisor |= (UINT32) SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_LOW);
|
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & ~B_UART_LCR_DLAB));
|
|
if (CurrentDivisor != Divisor) {
|
|
Initialized = FALSE;
|
|
}
|
|
if (Initialized) {
|
|
return RETURN_SUCCESS;
|
|
}
|
|
|
|
//
|
|
// Wait for the serial port to be ready.
|
|
// Verify that both the transmit FIFO and the shift register are empty.
|
|
//
|
|
while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
|
|
|
|
//
|
|
// Configure baud rate
|
|
//
|
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, B_UART_LCR_DLAB);
|
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8) (Divisor >> 8));
|
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8) (Divisor & 0xff));
|
|
|
|
//
|
|
// Clear DLAB and configure Data Bits, Parity, and Stop Bits.
|
|
// Strip reserved bits from PcdSerialLineControl
|
|
//
|
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(PcdGet8 (PcdSerialLineControl) & 0x3F));
|
|
|
|
//
|
|
// Enable and reset FIFOs
|
|
// Strip reserved bits from PcdSerialFifoControl
|
|
//
|
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, 0x00);
|
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));
|
|
|
|
//
|
|
// Put Modem Control Register(MCR) into its reset state of 0x00.
|
|
//
|
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00);
|
|
|
|
return RETURN_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
Write data from buffer to serial device.
|
|
|
|
Writes NumberOfBytes data bytes from Buffer to the serial device.
|
|
The number of bytes actually written to the serial device is returned.
|
|
If the return value is less than NumberOfBytes, then the write operation failed.
|
|
|
|
If Buffer is NULL, then ASSERT().
|
|
|
|
If NumberOfBytes is zero, then return 0.
|
|
|
|
@param Buffer Pointer to the data buffer to be written.
|
|
@param NumberOfBytes Number of bytes to written to the serial device.
|
|
|
|
@retval 0 NumberOfBytes is 0.
|
|
@retval >0 The number of bytes written to the serial device.
|
|
If this value is less than NumberOfBytes, then the read operation failed.
|
|
|
|
**/
|
|
UINTN
|
|
EFIAPI
|
|
SerialPortWrite (
|
|
IN UINT8 *Buffer,
|
|
IN UINTN NumberOfBytes
|
|
)
|
|
{
|
|
UINTN SerialRegisterBase;
|
|
UINTN Result;
|
|
UINTN Index;
|
|
UINTN FifoSize;
|
|
|
|
if (Buffer == NULL) {
|
|
return 0;
|
|
}
|
|
|
|
SerialRegisterBase = GetSerialRegisterBase ();
|
|
if (SerialRegisterBase ==0) {
|
|
return 0;
|
|
}
|
|
|
|
if (NumberOfBytes == 0) {
|
|
//
|
|
// Flush the hardware
|
|
//
|
|
|
|
//
|
|
// Wait for both the transmit FIFO and shift register empty.
|
|
//
|
|
while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
|
|
|
|
//
|
|
// Wait for the hardware flow control signal
|
|
//
|
|
while (!SerialPortWritable (SerialRegisterBase));
|
|
return 0;
|
|
}
|
|
|
|
//
|
|
// Compute the maximum size of the Tx FIFO
|
|
//
|
|
FifoSize = 1;
|
|
if ((PcdGet8 (PcdSerialFifoControl) & B_UART_FCR_FIFOE) != 0) {
|
|
if ((PcdGet8 (PcdSerialFifoControl) & B_UART_FCR_FIFO64) == 0) {
|
|
FifoSize = 16;
|
|
} else {
|
|
FifoSize = PcdGet32 (PcdSerialExtendedTxFifoSize);
|
|
}
|
|
}
|
|
|
|
Result = NumberOfBytes;
|
|
while (NumberOfBytes != 0) {
|
|
//
|
|
// Wait for the serial port to be ready, to make sure both the transmit FIFO
|
|
// and shift register empty.
|
|
//
|
|
while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_TEMT) == 0);
|
|
|
|
//
|
|
// Fill then entire Tx FIFO
|
|
//
|
|
for (Index = 0; Index < FifoSize && NumberOfBytes != 0; Index++, NumberOfBytes--, Buffer++) {
|
|
//
|
|
// Wait for the hardware flow control signal
|
|
//
|
|
while (!SerialPortWritable (SerialRegisterBase));
|
|
|
|
//
|
|
// Write byte to the transmit buffer.
|
|
//
|
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_TXBUF, *Buffer);
|
|
}
|
|
}
|
|
return Result;
|
|
}
|
|
|
|
/**
|
|
Reads data from a serial device into a buffer.
|
|
|
|
@param Buffer Pointer to the data buffer to store the data read from the serial device.
|
|
@param NumberOfBytes Number of bytes to read from the serial device.
|
|
|
|
@retval 0 NumberOfBytes is 0.
|
|
@retval >0 The number of bytes read from the serial device.
|
|
If this value is less than NumberOfBytes, then the read operation failed.
|
|
|
|
**/
|
|
UINTN
|
|
EFIAPI
|
|
SerialPortRead (
|
|
OUT UINT8 *Buffer,
|
|
IN UINTN NumberOfBytes
|
|
)
|
|
{
|
|
UINTN SerialRegisterBase;
|
|
UINTN Result;
|
|
UINT8 Mcr;
|
|
|
|
if (NULL == Buffer) {
|
|
return 0;
|
|
}
|
|
|
|
SerialRegisterBase = GetSerialRegisterBase ();
|
|
if (SerialRegisterBase ==0) {
|
|
return 0;
|
|
}
|
|
|
|
Mcr = (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS);
|
|
|
|
for (Result = 0; NumberOfBytes-- != 0; Result++, Buffer++) {
|
|
//
|
|
// Wait for the serial port to have some data.
|
|
//
|
|
while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_RXRDY) == 0) {
|
|
if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
|
|
//
|
|
// Set RTS to let the peer send some data
|
|
//
|
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(Mcr | B_UART_MCR_RTS));
|
|
}
|
|
}
|
|
if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
|
|
//
|
|
// Clear RTS to prevent peer from sending data
|
|
//
|
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr);
|
|
}
|
|
|
|
//
|
|
// Read byte from the receive buffer.
|
|
//
|
|
*Buffer = SerialPortReadRegister (SerialRegisterBase, R_UART_RXBUF);
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
|
|
/**
|
|
Polls a serial device to see if there is any data waiting to be read.
|
|
|
|
Polls aserial device to see if there is any data waiting to be read.
|
|
If there is data waiting to be read from the serial device, then TRUE is returned.
|
|
If there is no data waiting to be read from the serial device, then FALSE is returned.
|
|
|
|
@retval TRUE Data is waiting to be read from the serial device.
|
|
@retval FALSE There is no data waiting to be read from the serial device.
|
|
|
|
**/
|
|
BOOLEAN
|
|
EFIAPI
|
|
SerialPortPoll (
|
|
VOID
|
|
)
|
|
{
|
|
UINTN SerialRegisterBase;
|
|
|
|
SerialRegisterBase = GetSerialRegisterBase ();
|
|
if (SerialRegisterBase ==0) {
|
|
return FALSE;
|
|
}
|
|
|
|
//
|
|
// Read the serial port status
|
|
//
|
|
if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_RXRDY) != 0) {
|
|
if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
|
|
//
|
|
// Clear RTS to prevent peer from sending data
|
|
//
|
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS));
|
|
}
|
|
return TRUE;
|
|
}
|
|
|
|
if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
|
|
//
|
|
// Set RTS to let the peer send some data
|
|
//
|
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) | B_UART_MCR_RTS));
|
|
}
|
|
|
|
return FALSE;
|
|
}
|