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https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
168 lines
6.2 KiB
C
168 lines
6.2 KiB
C
/*++
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Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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Gpio.h
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Abstract:
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EFI 2.0 PEIM to provide platform specific information to other
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modules and to do some platform specific initialization.
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--*/
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#ifndef _PEI_GPIO_H
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#define _PEI_GPIO_H
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//#include "Efi.h"
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//#include "EfiCommonLib.h"
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//#include "Pei.h"
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//#include "Numbers.h"
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////
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//// GPIO Register Settings for BeaverBridge (FFVS) (Cedarview/Tigerpoint)
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////
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//// Field Descriptions:
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//// USE: Defines the pin's usage model: GPIO (G) or Native (N) mode.
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//// I/O: Defines whether GPIOs are inputs (I) or outputs (O).
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//// (Note: Only meaningful for pins used as GPIOs.)
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//// LVL: This field gives you the initial value for "output" GPIO's.
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//// (Note: The output level is dependent upon whether the pin is inverted.)
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//// INV: Defines whether Input GPIOs activation level is inverted.
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//// (Note: Only affects the level sent to the GPE logic and does not
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//// affect the level read through the GPIO registers.)
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////
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//// Notes:
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//// 1. BoardID is GPIO [8:38:34]
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////
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////Signal UsedAs USE I/O LVL INV
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////--------------------------------------------------------------------------
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////GPIO0 Nonfunction G O H -
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////GPIO1 SMC_RUNTIME_SCI# G I - I
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////PIRQE#/GPIO2 Nonfunction G O H -
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////PIRQF#/GPIO3 Nonfunction G O H -
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////PIRQG#/GPIO4 Nonfunction G O H -
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////PIRQH#/GPIO5 Nonfunction G O H -
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////GPIO6 unused G O L -
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////GPIO7 unused G O L -
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////GPIO8 BOARD ID2 G I - -
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////GPIO9 unused G O L -
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////GPIO10 SMC_EXTSMI# G I - I
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////GPIO11 Nonfunction G O H -
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////GPIO12 unused G O L -
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////GPIO13 SMC_WAKE_SCI# G I - I
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////GPIO14 unused G O L -
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////GPIO15 unused G O L -
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////GPIO16 PM_DPRSLPVR N - - -
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////GNT5#/GPIO17 GNT5# N - - -
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////STPPCI#/GPIO18 PM_STPPCI# N - - -
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////STPCPU#/GPIO20 PM_STPCPU# N - - -
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////GPIO22 CRT_RefClk G I - -
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////GPIO23 unused G O L -
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////GPIO24 unused G O L -
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////GPIO25 DMI strap G O L -
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////GPIO26 unused G O L -
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////GPIO27 unused G O L -
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////GPIO28 RF_KILL# G O H -
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////OC5#/GPIO29 OC N - - -
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////OC6#/GPIO30 OC N - - -
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////OC7#/GPIO31 OC N - - -
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////CLKRUN#/GPIO32 PM_CLKRUN# N - - -
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////GPIO33 NC G O L -
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////GPIO34 BOARD ID0 G I - -
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////GPIO36 unused G O L -
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////GPIO38 BOARD ID1 G I - -
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////GPIO39 unused G O L -
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////GPIO48 unused G O L -
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////CPUPWRGD/GPIO49 H_PWRGD N - - -
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//
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//#define GPIO_USE_SEL_VAL 0x1FC0FFFF //GPIO1, 10, 13 is EC signal
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//#define GPIO_USE_SEL2_VAL 0x000100D6
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//#define GPIO_IO_SEL_VAL 0x00402502
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//#define GPIO_IO_SEL2_VAL 0x00000044
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//#define GPIO_LVL_VAL 0x1800083D
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//#define GPIO_LVL2_VAL 0x00000000
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//#define GPIO_INV_VAL 0x00002402
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//#define GPIO_BLNK_VAL 0x00000000
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//#define ICH_GPI_ROUTE (ICH_GPI_ROUTE_SCI(13) | ICH_GPI_ROUTE_SCI(1))
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//
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// GPIO Register Settings for CedarRock and CedarFalls platforms
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//
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// GPIO Register Settings for NB10_CRB
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//---------------------------------------------------------------------------------
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//Signal Used As USE I/O LVL
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//---------------------------------------------------------------------------------
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//
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// GPIO0 FP_AUDIO_DETECT G I
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// GPIO1 SMC_RUNTIME_SCI# G I
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// GPIO2 INT_PIRQE_N N I
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// GPIO3 INT_PIRQF_N N I
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// GPIO4 INT_PIRQG_N N I
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// GPIO5 INT_PIRQH_N N I
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// GPIO6
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// GPIO7
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// GPIO8
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// GPIO9 LPC_SIO_PME G I
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// GPIO10 SMC_EXTSMI_N G I
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// GPIO11 SMBALERT- pullup N
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// GPIO12 ICH_GP12 G I
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// GPIO13 SMC_WAKE_SCI_N G I
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// GPIO14 LCD_PID0 G O H
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// GPIO15 CONFIG_MODE_N G I
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// GPIO16 PM_DPRSLPVR N
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// GPIO17 SPI_SELECT_STRAP1
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// /L_BKLTSEL0_N G I
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// GPIO18 PM_STPPCI_N N
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// GPIO19
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// GPIO20 PM_STPCPU_N N
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// GPIO21
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// GPIO22 REQ4B G I
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// GPIO23 L_DRQ1_N N
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// GPIO24 CRB_SV_DET_N G O H
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// GPIO25 DMI strap
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// / L_BKLTSEL1_N G O H
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// GPIO26 LCD_PID1 G O H
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// GPIO27 TPEV_DDR3L_DETECT G O H
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// GPIO28 RF_KILL G O H:enable
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// GPIO29 OC N
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// GPIO30 OC N
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// GPIO31 OC N
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// GPIO32 PM_CLKRUN_N Native
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// GPIO33 MFG_MODE_N G I
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// GPIO34 BOARD ID0 G I
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// GPIO35
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// GPIO36 SV_SET_UP G O H
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// GPIO37
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// GPIO38 BOARD ID1 G I
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// GPIO39 BOARD ID2 G I
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// GPIO48 FLASH_SEL0 N
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// GPIO49 H_PWRGD N
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#define ICH_GPI_ROUTE_SMI(Gpio) ((( 0 << ((Gpio * 2) + 1)) | (1 << (Gpio * 2))))
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#define ICH_GPI_ROUTE_SCI(Gpio) ((( 1 << ((Gpio * 2) + 1)) | (0 << (Gpio * 2))))
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#define GPIO_USE_SEL_VAL 0X1F42F7C3
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#define GPIO_USE_SEL2_VAL 0X000000D6
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#define GPIO_IO_SEL_VAL 0X1042B73F
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#define GPIO_IO_SEL2_VAL 0X000100C6
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#define GPIO_LVL_VAL 0X1F15F601
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#define GPIO_LVL2_VAL 0X000200D7
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#define GPIO_INV_VAL 0x00002602
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#define GPIO_BLNK_VAL 0x00040000
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#define ICH_GPI_ROUTE (ICH_GPI_ROUTE_SCI(13) | ICH_GPI_ROUTE_SCI(1))
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#endif
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