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4ae5165ce6
Signed-off-by: lzeng14 Reviewed-by: lgao4 git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12151 6f19259b-4bc3-4df7-8a09-765794883524
277 lines
9.2 KiB
C
277 lines
9.2 KiB
C
/** @file
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A Dxe Timer Library implementation which uses the Time Stamp Counter in the processor.
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For Pentium 4 processors, Intel Xeon processors (family [0FH], models [03H and higher]);
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for Intel Core Solo and Intel Core Duo processors (family [06H], model [0EH]);
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for the Intel Xeon processor 5100 series and Intel Core 2 Duo processors (family [06H], model [0FH]);
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for Intel Core 2 and Intel Xeon processors (family [06H], display_model [17H]);
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for Intel Atom processors (family [06H], display_model [1CH]):
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the time-stamp counter increments at a constant rate.
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That rate may be set by the maximum core-clock to bus-clock ratio of the processor or may be set by
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the maximum resolved frequency at which the processor is booted. The maximum resolved frequency may
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differ from the maximum qualified frequency of the processor.
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The specific processor configuration determines the behavior. Constant TSC behavior ensures that the
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duration of each clock tick is uniform and supports the use of the TSC as a wall clock timer even if
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the processor core changes frequency. This is the architectural behavior moving forward.
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A Processor's support for invariant TSC is indicated by CPUID.0x80000007.EDX[8].
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Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <PiDxe.h>
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#include <Ich/GenericIch.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/TimerLib.h>
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#include <Library/BaseLib.h>
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#include <Library/IoLib.h>
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#include <Library/PciLib.h>
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#include <Library/PcdLib.h>
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#include <Library/UefiLib.h>
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#include <Library/DebugLib.h>
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#include <Guid/TscFrequency.h>
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UINT64 mTscFrequency;
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/** The constructor function determines the actual TSC frequency.
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First, Get TSC frequency from system configuration table with TSC frequency GUID,
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if the table is not found, install it.
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The TSC counting frequency is determined by comparing how far it counts
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during a 1ms period as determined by the ACPI timer. The ACPI timer is
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used because it counts at a known frequency.
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If ACPI I/O space not enabled, this function will enable it. Then the
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TSC is sampled, followed by waiting for 3579 clocks of the ACPI timer, or 1ms.
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The TSC is then sampled again. The difference multiplied by 1000 is the TSC
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frequency. There will be a small error because of the overhead of reading
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the ACPI timer. An attempt is made to determine and compensate for this error.
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This function will always return EFI_SUCCESS.
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@param ImageHandle The firmware allocated handle for the EFI image.
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@param SystemTable A pointer to the EFI System Table.
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@retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
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**/
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EFI_STATUS
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EFIAPI
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DxeTscTimerLibConstructor (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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UINT64 *TscFrequency;
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UINT64 StartTSC;
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UINT64 EndTSC;
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UINT32 TimerAddr;
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UINT32 Ticks;
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//
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// Get TSC frequency from system configuration table with TSC frequency GUID.
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//
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Status = EfiGetSystemConfigurationTable (&gEfiTscFrequencyGuid, (VOID **) &TscFrequency);
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if (Status == EFI_SUCCESS) {
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mTscFrequency = *TscFrequency;
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return EFI_SUCCESS;
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}
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//
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// TSC frequency GUID system configuration table is not found, install it.
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//
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//
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// If ACPI I/O space is not enabled yet, program ACPI I/O base address and enable it.
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//
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if ((PciRead8 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_CNT)) & B_ICH_LPC_ACPI_CNT_ACPI_EN) == 0) {
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PciWrite16 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_BASE), PcdGet16 (PcdPerfPkgAcpiIoPortBaseAddress));
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PciOr8 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_CNT), B_ICH_LPC_ACPI_CNT_ACPI_EN);
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}
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//
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// ACPI I/O space should be enabled now, locate the ACPI Timer.
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// ACPI I/O base address maybe have be initialized by other driver with different value,
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// So get it from PCI space directly.
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//
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TimerAddr = ((PciRead16 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_BASE))) & B_ICH_LPC_ACPI_BASE_BAR) + R_ACPI_PM1_TMR;
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Ticks = IoRead32 (TimerAddr) + (3579); // Set Ticks to 1ms in the future
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StartTSC = AsmReadTsc(); // Get base value for the TSC
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//
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// Wait until the ACPI timer has counted 1ms.
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// Timer wrap-arounds are handled correctly by this function.
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// When the current ACPI timer value is greater than 'Ticks', the while loop will exit.
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//
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while (((Ticks - IoRead32 (TimerAddr)) & BIT23) == 0) {
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CpuPause();
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}
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EndTSC = AsmReadTsc(); // TSC value 1ms later
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Status = gBS->AllocatePool (EfiBootServicesData, sizeof (UINT64), &TscFrequency);
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ASSERT_EFI_ERROR (Status);
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*TscFrequency = MultU64x32 (
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(EndTSC - StartTSC), // Number of TSC counts in 1ms
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1000 // Number of ms in a second
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);
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//
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// TscFrequency now points to the number of TSC counts per second, install system configuration table for it.
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//
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gBS->InstallConfigurationTable (&gEfiTscFrequencyGuid, TscFrequency);
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mTscFrequency = *TscFrequency;
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return EFI_SUCCESS;
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}
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/** Stalls the CPU for at least the given number of ticks.
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Stalls the CPU for at least the given number of ticks. It's invoked by
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MicroSecondDelay() and NanoSecondDelay().
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@param[in] Delay A period of time to delay in ticks.
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**/
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VOID
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InternalX86Delay (
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IN UINT64 Delay
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)
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{
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UINT64 Ticks;
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//
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// The target timer count is calculated here
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//
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Ticks = AsmReadTsc() + Delay;
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//
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// Wait until time out
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// Timer wrap-arounds are NOT handled correctly by this function.
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// Thus, this function must be called within 10 years of reset since
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// Intel guarantees a minimum of 10 years before the TSC wraps.
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//
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while (AsmReadTsc() <= Ticks) CpuPause();
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}
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/** Stalls the CPU for at least the specified number of MicroSeconds.
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@param[in] MicroSeconds The minimum number of microseconds to delay.
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@return The value of MicroSeconds input.
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**/
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UINTN
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EFIAPI
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MicroSecondDelay (
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IN UINTN MicroSeconds
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)
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{
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InternalX86Delay (
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DivU64x32 (
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MultU64x64 (
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mTscFrequency,
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MicroSeconds
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),
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1000000u
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)
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);
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return MicroSeconds;
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}
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/** Stalls the CPU for at least the specified number of NanoSeconds.
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@param[in] NanoSeconds The minimum number of nanoseconds to delay.
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@return The value of NanoSeconds input.
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**/
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UINTN
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EFIAPI
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NanoSecondDelay (
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IN UINTN NanoSeconds
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)
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{
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InternalX86Delay (
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DivU64x32 (
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MultU64x32 (
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mTscFrequency,
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(UINT32)NanoSeconds
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),
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1000000000u
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)
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);
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return NanoSeconds;
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}
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/** Retrieves the current value of the 64-bit free running Time-Stamp counter.
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The time-stamp counter (as implemented in the P6 family, Pentium, Pentium M,
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Pentium 4, Intel Xeon, Intel Core Solo and Intel Core Duo processors and
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later processors) is a 64-bit counter that is set to 0 following a RESET of
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the processor. Following a RESET, the counter increments even when the
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processor is halted by the HLT instruction or the external STPCLK# pin. Note
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that the assertion of the external DPSLP# pin may cause the time-stamp
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counter to stop.
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The properties of the counter can be retrieved by the
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GetPerformanceCounterProperties() function.
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@return The current value of the free running performance counter.
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**/
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UINT64
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EFIAPI
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GetPerformanceCounter (
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VOID
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)
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{
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return AsmReadTsc();
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}
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/** Retrieves the 64-bit frequency in Hz and the range of performance counter
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values.
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If StartValue is not NULL, then the value that the performance counter starts
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with, 0x0, is returned in StartValue. If EndValue is not NULL, then the value
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that the performance counter end with, 0xFFFFFFFFFFFFFFFF, is returned in
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EndValue.
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The 64-bit frequency of the performance counter, in Hz, is always returned.
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To determine average processor clock frequency, Intel recommends the use of
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EMON logic to count processor core clocks over the period of time for which
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the average is required.
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@param[out] StartValue Pointer to where the performance counter's starting value is saved, or NULL.
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@param[out] EndValue Pointer to where the performance counter's ending value is saved, or NULL.
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@return The frequency in Hz.
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**/
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UINT64
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EFIAPI
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GetPerformanceCounterProperties (
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OUT UINT64 *StartValue, OPTIONAL
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OUT UINT64 *EndValue OPTIONAL
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)
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{
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if (StartValue != NULL) {
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*StartValue = 0;
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}
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if (EndValue != NULL) {
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*EndValue = 0xFFFFFFFFFFFFFFFFull;
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}
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return mTscFrequency;
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}
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