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	In the former memory model, the UEFI firmware was expected to be located at the top of the system memory. Stacks & Pi memory regions were set below the firmware. On some platform, the UEFI firmware could be shadowed by the ROM firmware (case of the BeagleBoard) and in some cases the firmware is copied at the beginning of the system memory. With this new memory model, stack and Pi/DXE memory regions are set at the top of the system memory wherever the UEFI firmware is located in the memory map. Because DXE core does not support shadowed firmwares, the system memory covered by the UEFI firmware is marked as 'Non Present' to avoid to be overlapped by DXE allocations. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11992 6f19259b-4bc3-4df7-8a09-765794883524
		
			
				
	
	
		
			102 lines
		
	
	
		
			3.3 KiB
		
	
	
	
		
			NASM
		
	
	
	
	
	
			
		
		
	
	
			102 lines
		
	
	
		
			3.3 KiB
		
	
	
	
		
			NASM
		
	
	
	
	
	
//
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//  Copyright (c) 2011, ARM Limited. All rights reserved.
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//
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//  This program and the accompanying materials
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//  are licensed and made available under the terms and conditions of the BSD License
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//  which accompanies this distribution.  The full text of the license may be found at
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//  http://opensource.org/licenses/bsd-license.php
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//
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//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//
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#include <AsmMacroIoLib.h>
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#include <Base.h>
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#include <Library/PcdLib.h>
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#include <AutoGen.h>
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  INCLUDE AsmMacroIoLib.inc
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  IMPORT  CEntryPoint
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  EXPORT  _ModuleEntryPoint
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  PRESERVE8
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  AREA    PrePiCoreEntryPoint, CODE, READONLY
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StartupAddr        DCD      CEntryPoint
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_ModuleEntryPoint
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  // Identify CPU ID
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  mrc   p15, 0, r0, c0, c0, 5
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  and   r0, #0xf
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_SetSVCMode
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  // Enter SVC mode
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  mov     r1, #0x13|0x80|0x40
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  msr     CPSR_c, r1
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// Check if we can install the size at the top of the System Memory or if we need
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// to install the stacks at the bottom of the Firmware Device (case the FD is located
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// at the top of the DRAM)
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_SetupStackPosition
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  // Compute Top of System Memory
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  LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryBase), r1)
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  LoadConstantToReg (FixedPcdGet32(PcdSystemMemorySize), r2)
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  add   r1, r1, r2      // r1 = SystemMemoryTop = PcdSystemMemoryBase + PcdSystemMemorySize
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  // Calculate Top of the Firmware Device
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  LoadConstantToReg (FixedPcdGet32(PcdNormalFdBaseAddress), r2)
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  LoadConstantToReg (FixedPcdGet32(PcdNormalFdSize), r3)
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  add   r3, r3, r2      // r4 = FdTop = PcdNormalFdBaseAddress + PcdNormalFdSize
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  // UEFI Memory Size (stacks are allocated in this region)
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  LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryUefiRegionSize), r4)
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  //
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  // Reserve the memory for the UEFI region (contain stacks on its top)
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  //
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  // Calculate how much space there is between the top of the Firmware and the Top of the System Memory
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  subs	r5, r1, r3		// r5 = SystemMemoryTop - FdTop
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  bmi	_SetupStack		// Jump if negative (FdTop > SystemMemoryTop)
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  cmp	r5, r4
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  bge	_SetupStack
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  // Case the top of stacks is the FdBaseAddress
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  mov	r1, r2
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_SetupStack
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  // Compute Base of Normal stacks for CPU Cores
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  LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackSize), r5)
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  mul   r3, r0, r5      // r3 = core_id * stack_size = offset from the stack base
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  sub   sp, r1, r3      // r3 = (SystemMemoryTop|FdBaseAddress) - StackOffset = TopOfStack
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  // Calculate the Base of the UEFI Memory
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  sub	r1, r1, r4
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  // Only allocate memory for global variables at top of the primary core stack
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  cmp   r0, #0
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  bne   _PrepareArguments
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_AllocateGlobalPrePiVariables
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  // Reserve top of the stack for Global PEI Variables (eg: PeiServicesTablePointer)
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  LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r4)
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  // The reserved place must be 8-bytes aligned for pushing 64-bit variable on the stack
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  and   r5, r4, #7
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  rsb   r5, r5, #8
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  add   r4, r4, r5
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  sub   sp, sp, r4
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_PrepareArguments
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  // Move sec startup address into a data register
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  // Ensure we're jumping to FV version of the code (not boot remapped alias)
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  ldr   r2, StartupAddr
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  // Jump to PrePiCore C code
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  //    r0 = core_id
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  //    r1 = UefiMemoryBase
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  blx   r2
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  END
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