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2e01a5c128
The definition of IA32_MAP_ATTRIBUTE has 64 bits, and one of the bit field PageTableBaseAddress is from bit 12 to bit 52. This means if the compiler treats the 64bits value as two UINT32 value, the field PageTableBaseAddress spans two UINT32 value. That's why when building in NOOPT mode in IA32, the below issue is noticed: unresolved external symbol __allshl This patch fix the build failure by seperate field PageTableBaseAddress into two fields, make sure no field spans two UINT32 value. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Ray Ni <ray.ni@intel.com>
232 lines
8.8 KiB
C
232 lines
8.8 KiB
C
/** @file
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Internal header for CpuPageTableLib.
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Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef CPU_PAGE_TABLE_H_
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#define CPU_PAGE_TABLE_H_
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#include <Base.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/CpuPageTableLib.h>
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#define IA32_PE_BASE_ADDRESS_MASK_40 0xFFFFFFFFFF000ull
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#define IA32_PE_BASE_ADDRESS_MASK_39 0xFFFFFFFFFE000ull
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#define REGION_LENGTH(l) LShiftU64 (1, (l) * 9 + 3)
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typedef enum {
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Pte = 1,
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Pde = 2,
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Pdpte = 3,
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Pml4 = 4,
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Pml5 = 5
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} IA32_PAGE_LEVEL;
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typedef struct {
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UINT32 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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UINT32 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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UINT32 UserSupervisor : 1; // 0 = Supervisor, 1=User
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UINT32 Reserved0 : 29;
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UINT32 Reserved1 : 31;
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UINT32 Nx : 1; // No Execute bit
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} IA32_PAGE_COMMON_ENTRY;
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///
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/// Format of a non-leaf entry that references a page table entry
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///
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typedef union {
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struct {
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UINT32 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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UINT32 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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UINT32 UserSupervisor : 1; // 0 = Supervisor, 1=User
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UINT32 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT32 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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UINT32 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT32 Available0 : 1; // Ignored
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UINT32 MustBeZero : 1; // Must Be Zero
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UINT32 Available2 : 4; // Ignored
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UINT32 PageTableBaseAddressLow : 20; // Page Table Base Address Low
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UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address High
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UINT32 Available3 : 11; // Ignored
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UINT32 Nx : 1; // No Execute bit
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} Bits;
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UINT64 Uint64;
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} IA32_PAGE_NON_LEAF_ENTRY;
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#define IA32_PNLE_PAGE_TABLE_BASE_ADDRESS(pa) ((pa)->Uint64 & IA32_PE_BASE_ADDRESS_MASK_40)
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///
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/// Format of a PML5 Entry (PML5E) that References a PML4 Table
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///
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typedef IA32_PAGE_NON_LEAF_ENTRY IA32_PML5E;
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///
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/// Format of a PML4 Entry (PML4E) that References a Page-Directory-Pointer Table
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///
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typedef IA32_PAGE_NON_LEAF_ENTRY IA32_PML4E;
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///
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/// Format of a Page-Directory-Pointer-Table Entry (PDPTE) that References a Page Directory
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///
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typedef IA32_PAGE_NON_LEAF_ENTRY IA32_PDPTE;
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///
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/// Format of a Page-Directory Entry that References a Page Table
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///
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typedef IA32_PAGE_NON_LEAF_ENTRY IA32_PDE;
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///
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/// Format of a leaf entry that Maps a 1-Gbyte or 2-MByte Page
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///
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typedef union {
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struct {
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UINT32 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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UINT32 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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UINT32 UserSupervisor : 1; // 0 = Supervisor, 1=User
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UINT32 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT32 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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UINT32 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT32 Dirty : 1; // 0 = Not dirty, 1 = Dirty (set by CPU)
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UINT32 MustBeOne : 1; // Page Size. Must Be One
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UINT32 Global : 1; // 0 = Not global, 1 = Global (if CR4.PGE = 1)
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UINT32 Available1 : 3; // Ignored
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UINT32 Pat : 1; // PAT
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UINT32 PageTableBaseAddressLow : 19; // Page Table Base Address Low
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UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address High
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UINT32 Available3 : 7; // Ignored
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UINT32 ProtectionKey : 4; // Protection key
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UINT32 Nx : 1; // No Execute bit
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} Bits;
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UINT64 Uint64;
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} IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE;
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#define IA32_PLEB_PAGE_TABLE_BASE_ADDRESS(pa) ((pa)->Uint64 & IA32_PE_BASE_ADDRESS_MASK_39)
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///
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/// Format of a Page-Directory Entry that Maps a 2-MByte Page
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///
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typedef IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE IA32_PDE_2M;
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///
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/// Format of a Page-Directory-Pointer-Table Entry (PDPTE) that Maps a 1-GByte Page
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///
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typedef IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE IA32_PDPTE_1G;
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///
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/// Format of a Page-Table Entry that Maps a 4-KByte Page
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///
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typedef union {
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struct {
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UINT32 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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UINT32 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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UINT32 UserSupervisor : 1; // 0 = Supervisor, 1=User
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UINT32 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT32 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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UINT32 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT32 Dirty : 1; // 0 = Not dirty, 1 = Dirty (set by CPU)
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UINT32 Pat : 1; // PAT
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UINT32 Global : 1; // 0 = Not global, 1 = Global (if CR4.PGE = 1)
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UINT32 Available1 : 3; // Ignored
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UINT32 PageTableBaseAddressLow : 20; // Page Table Base Address Low
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UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address High
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UINT32 Available3 : 7; // Ignored
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UINT32 ProtectionKey : 4; // Protection key
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UINT32 Nx : 1; // No Execute bit
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} Bits;
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UINT64 Uint64;
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} IA32_PTE_4K;
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#define IA32_PTE4K_PAGE_TABLE_BASE_ADDRESS(pa) ((pa)->Uint64 & IA32_PE_BASE_ADDRESS_MASK_40)
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///
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/// Format of a Page-Directory-Pointer-Table Entry (PDPTE) that References a Page Directory (32bit PAE specific)
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///
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typedef union {
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struct {
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UINT32 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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UINT32 MustBeZero : 2; // Must Be Zero
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UINT32 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT32 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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UINT32 MustBeZero2 : 4; // Must Be Zero
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UINT32 Available : 3; // Ignored
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UINT32 PageTableBaseAddressLow : 20; // Page Table Base Address Low
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UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address High
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UINT32 MustBeZero3 : 12; // Must Be Zero
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} Bits;
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UINT64 Uint64;
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} IA32_PDPTE_PAE;
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typedef union {
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IA32_PAGE_NON_LEAF_ENTRY Pnle; // To access Pml5, Pml4, Pdpte and Pde.
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IA32_PML5E Pml5;
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IA32_PML4E Pml4;
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IA32_PDPTE Pdpte;
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IA32_PDE Pde;
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IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE PleB; // to access Pdpte1G and Pde2M.
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IA32_PDPTE_1G Pdpte1G;
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IA32_PDE_2M Pde2M;
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IA32_PTE_4K Pte4K;
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IA32_PDPTE_PAE PdptePae;
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IA32_PAGE_COMMON_ENTRY Pce; // To access all common bits in above entries.
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UINT64 Uint64;
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UINTN Uintn;
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} IA32_PAGING_ENTRY;
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/**
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Return TRUE when the page table entry is a leaf entry that points to the physical address memory.
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Return FALSE when the page table entry is a non-leaf entry that points to the page table entries.
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@param[in] PagingEntry Pointer to the page table entry.
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@param[in] Level Page level where the page table entry resides in.
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@retval TRUE It's a leaf entry.
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@retval FALSE It's a non-leaf entry.
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**/
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BOOLEAN
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IsPle (
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IN IA32_PAGING_ENTRY *PagingEntry,
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IN UINTN Level
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);
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/**
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Return the attribute of a 2M/1G page table entry.
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@param[in] PleB Pointer to a 2M/1G page table entry.
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@param[in] ParentMapAttribute Pointer to the parent attribute.
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@return Attribute of the 2M/1G page table entry.
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**/
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UINT64
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PageTableLibGetPleBMapAttribute (
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IN IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE *PleB,
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IN IA32_MAP_ATTRIBUTE *ParentMapAttribute
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);
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/**
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Return the attribute of a non-leaf page table entry.
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@param[in] Pnle Pointer to a non-leaf page table entry.
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@param[in] ParentMapAttribute Pointer to the parent attribute.
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@return Attribute of the non-leaf page table entry.
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**/
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UINT64
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PageTableLibGetPnleMapAttribute (
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IN IA32_PAGE_NON_LEAF_ENTRY *Pnle,
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IN IA32_MAP_ATTRIBUTE *ParentMapAttribute
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);
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#endif
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