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fcea0fcb23
Problems have been encountered because some of the source files have execute permission set. This can cause git to report them as changed when they are checked out onto a file system with inherited permissions. This has been seen using Cygwin, MinGW and PowerShell Git. This patch makes no change to source file content, and only aims to correct the file modes/permissions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19787 6f19259b-4bc3-4df7-8a09-765794883524
63 lines
2.0 KiB
NASM
63 lines
2.0 KiB
NASM
//
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// Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//
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#include <AsmMacroIoLib.h>
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#include <Library/PcdLib.h>
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#include <Drivers/PL35xSmc.h>
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#include <AutoGen.h>
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INCLUDE AsmMacroIoLib.inc
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EXPORT PL35xSmcInitialize
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EXPORT PL35xSmcSetRefresh
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PRESERVE8
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AREA ModuleInitializeSMC, CODE, READONLY
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// IN r1 Smc Base Address
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// IN r2 Smc Configuration Start Address
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// IN r3 Smc Configuration End Address
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// NOTE: This code is been called before any stack has been setup. It means some registers
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// could be overwritten (case of 'r0')
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PL35xSmcInitialize
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// While (SmcConfigurationStart < SmcConfigurationEnd)
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cmp r2, r3
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blxge lr
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// Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)
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ldr r0, [r2, #0x4]
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str r0, [r1, #PL350_SMC_SET_CYCLES_OFFSET]
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// Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)
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ldr r0, [r2, #0x8]
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str r0, [r1, #PL350_SMC_SET_OPMODE_OFFSET]
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// Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers
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ldr r0, =PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE
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ldr r4, [r2, #0x0]
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orr r0, r0, r4
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str r0, [r1, #PL350_SMC_DIRECT_CMD_OFFSET]
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add r2, #0xC
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b PL35xSmcInitialize
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// IN r1 Smc Base Address
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// IN r2 Smc Refresh Period 0
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// IN r3 Smc Refresh Period 1
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PL35xSmcSetRefresh
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str r2, [r1, #PL350_SMC_REFRESH_0_OFFSET]
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str r3, [r1, #PL350_SMC_REFRESH_1_OFFSET]
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blx lr
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END
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