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807e2604ab
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14515 6f19259b-4bc3-4df7-8a09-765794883524
38 lines
1.3 KiB
ArmAsm
38 lines
1.3 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# CpuBreakpoint() for AArch64
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#
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# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
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# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php.
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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.text
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.p2align 2
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ASM_GLOBAL ASM_PFX(CpuBreakpoint)
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#/**
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# Generates a breakpoint on the CPU.
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#
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# Generates a breakpoint on the CPU. The breakpoint must be implemented such
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# that code can resume normal execution after the breakpoint.
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#
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#**/
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#VOID
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#EFIAPI
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#CpuBreakpoint (
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# VOID
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# );
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#
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ASM_PFX(CpuBreakpoint):
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svc 0xdbdb // Superviser exception. Takes 16bit arg -> Armv7 had 'swi' here.
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ret
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