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https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
527 lines
17 KiB
C
527 lines
17 KiB
C
/**
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Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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@file
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PchAccess.h
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@brief
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Macros that simplify accessing PCH devices's PCI registers.
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** NOTE ** these macros assume the PCH device is on BUS 0
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**/
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#ifndef _PCH_ACCESS_H_
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#define _PCH_ACCESS_H_
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#include "PchRegs.h"
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#include "PchCommonDefinitions.h"
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#ifndef STALL_ONE_MICRO_SECOND
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#define STALL_ONE_MICRO_SECOND 1
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#endif
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#ifndef STALL_ONE_SECOND
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#define STALL_ONE_SECOND 1000000
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#endif
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///
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/// Memory Mapped PCI Access macros
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///
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///
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/// PCI Device MM Base
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///
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#ifndef MmPciAddress
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#define MmPciAddress(Segment, Bus, Device, Function, Register) \
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((UINTN) PatchPcdGet64 (PcdPciExpressBaseAddress) + \
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(UINTN) (Bus << 20) + \
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(UINTN) (Device << 15) + \
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(UINTN) (Function << 12) + \
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(UINTN) (Register) \
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)
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#endif
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///
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/// Pch Controller PCI access macros
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///
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#define PCH_RCRB_BASE ( \
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MmioRead32 (MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_LPC, \
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PCI_FUNCTION_NUMBER_PCH_LPC), \
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R_PCH_LPC_RCBA)) & B_PCH_LPC_RCBA_BAR \
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)
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///
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/// Device 0x1b, Function 0
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///
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#define PchAzaliaPciCfg32(Register) \
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MmioRead32 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_AZALIA, \
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0, \
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Register) \
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)
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#define PchAzaliaPciCfg32Or(Register, OrData) \
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MmioOr32 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_AZALIA, \
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0, \
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Register), \
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OrData \
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)
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#define PchAzaliaPciCfg32And(Register, AndData) \
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MmioAnd32 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_AZALIA, \
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0, \
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Register), \
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AndData \
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)
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#define PchAzaliaPciCfg32AndThenOr(Register, AndData, OrData) \
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MmioAndThenOr32 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_AZALIA, \
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0, \
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Register), \
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OrData \
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)
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#define PchAzaliaPciCfg16(Register) \
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MmioRead16 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_AZALIA, \
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0, \
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Register) \
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)
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#define PchAzaliaPciCfg16Or(Register, OrData) \
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MmioOr16 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_AZALIA, \
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0, \
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Register), \
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OrData \
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)
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#define PchAzaliaPciCfg16And(Register, AndData) \
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MmioAnd16 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_AZALIA, \
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0, \
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Register), \
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AndData \
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)
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#define PchAzaliaPciCfg16AndThenOr(Register, AndData, OrData) \
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MmioAndThenOr16 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_AZALIA, \
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0, \
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Register), \
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AndData, \
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OrData \
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)
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#define PchAzaliaPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_AZALIA, 0, Register))
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#define PchAzaliaPciCfg8Or(Register, OrData) \
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MmioOr8 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_AZALIA, \
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0, \
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Register), \
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OrData \
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)
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#define PchAzaliaPciCfg8And(Register, AndData) \
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MmioAnd8 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_AZALIA, \
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0, \
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Register), \
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AndData \
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)
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#define PchAzaliaPciCfg8AndThenOr(Register, AndData, OrData) \
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MmioAndThenOr8 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_AZALIA, \
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0, \
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Register), \
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AndData, \
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OrData \
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)
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///
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/// Device 0x1f, Function 0
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///
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#define PchLpcPciCfg32(Register) MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))
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#define PchLpcMmioOr32 (Register, OrData) \
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MmioOr32 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_LPC, \
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0, \
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Register), \
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OrData \
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)
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#define PchLpcPciCfg32And(Register, AndData) \
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MmioAnd32 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_LPC, \
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0, \
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Register), \
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AndData \
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)
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#define PchLpcPciCfg32AndThenOr(Register, AndData, OrData) \
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MmioAndThenOr32 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_LPC, \
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0, \
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Register), \
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AndData, \
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OrData \
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)
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#define PchLpcPciCfg16(Register) MmioRead16 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))
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#define PchLpcPciCfg16Or(Register, OrData) \
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MmioOr16 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_LPC, \
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0, \
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Register), \
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OrData \
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)
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#define PchLpcPciCfg16And(Register, AndData) \
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MmioAndThenOr16 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_LPC, \
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0, \
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Register), \
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AndData \
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)
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#define PchLpcPciCfg16AndThenOr(Register, AndData, OrData) \
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MmioAndThenOr16 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_LPC, \
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0, \
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Register), \
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AndData, \
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OrData \
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)
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#define PchLpcPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))
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#define PchLpcPciCfg8Or(Register, OrData) \
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MmioOr8 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_LPC, \
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0, \
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Register), \
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OrData \
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)
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#define PchLpcPciCfg8And(Register, AndData) \
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MmioAnd8 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_LPC, \
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0, \
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Register), \
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AndData \
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)
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#define PchLpcPciCfg8AndThenOr(Register, AndData, OrData) \
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MmioAndThenOr8 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_LPC, \
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0, \
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Register), \
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AndData, \
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OrData \
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)
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///
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/// SATA device 0x13, Function 0
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///
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#define PchSataPciCfg32(Register) MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))
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#define PchSataPciCfg32Or(Register, OrData) \
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MmioOr32 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_SATA, \
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PCI_FUNCTION_NUMBER_PCH_SATA, \
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Register), \
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OrData \
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)
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#define PchSataPciCfg32And(Register, AndData) \
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MmioAnd32 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_SATA, \
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PCI_FUNCTION_NUMBER_PCH_SATA, \
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Register), \
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AndData \
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)
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#define PchSataPciCfg32AndThenOr(Register, AndData, OrData) \
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MmioAndThenOr32 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_SATA, \
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PCI_FUNCTION_NUMBER_PCH_SATA, \
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Register), \
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AndData, \
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OrData \
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)
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#define PchSataPciCfg16(Register) MmioRead16 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))
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#define PchSataPciCfg16Or(Register, OrData) \
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MmioOr16 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_SATA, \
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PCI_FUNCTION_NUMBER_PCH_SATA, \
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Register), \
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OrData \
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)
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#define PchSataPciCfg16And(Register, AndData) \
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MmioAndThenOr16 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_SATA, \
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PCI_FUNCTION_NUMBER_PCH_SATA, \
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Register), \
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AndData \
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)
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#define PchSataPciCfg16AndThenOr(Register, AndData, OrData) \
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MmioAndThenOr16 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_SATA, \
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PCI_FUNCTION_NUMBER_PCH_SATA, \
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Register), \
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AndData, \
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OrData \
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)
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#define PchSataPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))
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#define PchSataPciCfg8Or(Register, OrData) \
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MmioOr8 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_SATA, \
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PCI_FUNCTION_NUMBER_PCH_SATA, \
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Register), \
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OrData \
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)
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#define PchSataPciCfg8And(Register, AndData) \
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MmioAnd8 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_SATA, \
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PCI_FUNCTION_NUMBER_PCH_SATA, \
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Register), \
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AndData \
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)
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#define PchSataPciCfg8AndThenOr(Register, AndData, OrData) \
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MmioAndThenOr8 ( \
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MmPciAddress (0, \
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DEFAULT_PCI_BUS_NUMBER_PCH, \
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PCI_DEVICE_NUMBER_PCH_SATA, \
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PCI_FUNCTION_NUMBER_PCH_SATA, \
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Register), \
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AndData, \
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OrData \
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)
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///
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/// Root Complex Register Block
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///
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#define PchMmRcrb32(Register) MmioRead32 (PCH_RCRB_BASE + Register)
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#define PchMmRcrb32Or(Register, OrData) MmioOr32 (PCH_RCRB_BASE + Register, OrData)
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#define PchMmRcrb32And(Register, AndData) MmioAnd32 (PCH_RCRB_BASE + Register, AndData)
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#define PchMmRcrb32AndThenOr(Register, AndData, OrData) MmioAndThenOr32 (PCH_RCRB_BASE + Register, AndData, OrData)
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#define PchMmRcrb16(Register) MmioRead16 (PCH_RCRB_BASE + Register)
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#define PchMmRcrb16Or(Register, OrData) MmioOr16 (PCH_RCRB_BASE + Register, OrData)
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#define PchMmRcrb16And(Register, AndData) MmioAnd16 (PCH_RCRB_BASE + Register, AndData)
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#define PchMmRcrb16AndThenOr(Register, AndData, OrData) MmioAndThenOr16 (PCH_RCRB_BASE + Register, AndData, OrData)
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#define PchMmRcrb8(Register) MmioRead8 (PCH_RCRB_BASE + Register)
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#define PchMmRcrb8Or(Register, OrData) MmioOr8 (PCH_RCRB_BASE + Register, OrData)
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#define PchMmRcrb8And(Register, AndData) MmioAnd8 (PCH_RCRB_BASE + Register, AndData)
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#define PchMmRcrb8AndThenOr(Register, AndData, OrData) MmioAndThenOr8 (PCH_RCRB_BASE + Register, AndData, OrData)
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///
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/// Message Bus
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///
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///
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/// Message Bus Registers
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///
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#define MC_MCR 0x000000D0 // Cunit Message Control Register
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#define MC_MDR 0x000000D4 // Cunit Message Data Register
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#define MC_MCRX 0x000000D8 // Cunit Message Control Register Extension
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///
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/// Message Bus API
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///
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#define MSG_BUS_ENABLED 0x000000F0
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#define MSGBUS_MASKHI 0xFFFFFF00
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#define MSGBUS_MASKLO 0x000000FF
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#define MESSAGE_DWORD_EN BIT4 | BIT5 | BIT6 | BIT7
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#define PchMsgBusRead32(PortId, Register, Dbuff, ReadOpCode, WriteOpCode) \
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{ \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
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(Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
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}
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#define PchMsgBusAnd32(PortId, Register, Dbuff, AndData, ReadOpCode, WriteOpCode) \
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{ \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
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(Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) (Dbuff & AndData)); \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
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}
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#define PchMsgBusOr32(PortId, Register, Dbuff, OrData, ReadOpCode, WriteOpCode) \
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{ \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
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(Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) (Dbuff | OrData)); \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
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}
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#define PchMsgBusAndThenOr32(PortId, Register, Dbuff, AndData, OrData, ReadOpCode, WriteOpCode) \
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{ \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
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(Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) ((Dbuff & AndData) | OrData)); \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
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}
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typedef struct _PCH_MSG_BUS_TABLE_STRUCT {
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UINT32 PortId;
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UINT32 Address;
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UINT32 AndMask;
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UINT32 OrMask;
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UINT32 ReadOpCode;
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UINT32 WriteOpCode;
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} PCH_MSG_BUS_TABLE_STRUCT_TABLE_STRUCT;
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#ifndef _S3SUPPORT_
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#define _S3SUPPORT_
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UINTN MCRX;
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UINTN MCR;
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//
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// In S3 execute, we should follow the MSG BUS access procedure to restore the saving data.
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// To do so, we adopt READ ->> SAVE
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// Indirect IO access: (According BayTrail-M EDS chapter 3.6)
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// 1. Write Index port into MSG BUS_MCRX first.
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// 2. Write content to data register which is called MSG BUS_MDR.
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// 3. Send "message bus control" to complete the procedure.
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//
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#define S3BootScriptSaveMsgBusToMemWrite(PortId, Register, Dbuff, ReadOpCode, WriteOpCode) \
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{ \
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MCRX = (UINTN) Register & MSGBUS_MASKHI; \
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MCR = (UINTN) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN); \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) MCRX); \
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S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX),1, (VOID *) (UINTN) &MCRX); \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) MCR); \
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(Dbuff) = (UINT32) MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
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S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR),1, (VOID *) &Dbuff); \
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MCR = (UINTN) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN); \
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S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR),1, (VOID *) (UINTN) &MCR); \
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}
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//
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// This macro combines two function: 1. PchMsgBusAndThenOr32 () 2. S3 boot script save
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//
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#define PchMsgBusAndThenOr32AddToS3Save(PortId, Register, Dbuff, AndData, OrData, ReadOpCode, WriteOpCode) \
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{ \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
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(Dbuff) = (UINT32) MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) ((Dbuff & AndData) | OrData)); \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
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MCRX = (UINTN) Register & MSGBUS_MASKHI; \
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MCR = (UINTN) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN); \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) MCRX); \
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S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX),1,(VOID *) (UINTN) &MCRX); \
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MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) MCR); \
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(Dbuff) = (UINT32) MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
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S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR),1,(VOID *) &Dbuff); \
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MCR = (UINTN) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN); \
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S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR),1,(VOID *) (UINTN) &MCR); \
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|
}
|
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#endif
|
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#endif
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