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			https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
		
			
				
	
	
		
			56 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
			
		
		
	
	
			56 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
| /**************************************************************************;
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| ;*                                                                        *;
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| ;*                                                                        *;
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| ;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
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| ;*    Family of Customer Reference Boards.                                *;
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| ;*                                                                        *;
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| ;*                                                                        *;
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| ;*    Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved   *;
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| ;
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| ; This program and the accompanying materials are licensed and made available under
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| ; the terms and conditions of the BSD License that accompanies this distribution.
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| ; The full text of the license may be found at
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| ; http://opensource.org/licenses/bsd-license.php.
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| ;
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| ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| ;
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| ;*                                                                        *;
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| ;*                                                                        *;
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| ;**************************************************************************/
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| 
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| 
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| 
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| // NOTE:  The _PDC Implementation is out of the scope of this
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| // reference code.  Please see the latest Hyper-Threading Technology
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| // Reference Code for complete implementation details.
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| 
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| Scope(\_PR)
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| {
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|   Processor(CPU0,         // Unique name for Processor 0.
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|             1,                        // Unique ID for Processor 0.
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|             0x00,                 // CPU0 ACPI P_BLK address = ACPIBASE + 10h.
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|             0)                        // CPU0  P_BLK length = 6 bytes.
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|   {}
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| 
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|   Processor(CPU1,         // Unique name for Processor 1.
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|             2,                        // Unique ID for Processor 1.
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|             0x00,
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|             0)                    // CPU1 P_BLK length = 6 bytes.
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|   {}
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| 
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|   Processor(CPU2,         // Unique name for Processor 2.
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|             3,                        // Unique ID for Processor 2.
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|             0x00,
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|             0)                    // CPU2 P_BLK length = 6 bytes.
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|   {}
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| 
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|   Processor(CPU3,         // Unique name for Processor 3.
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|             4,                        // Unique ID for Processor 3.
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|             0x00,
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|             0)                    // CPU3 P_BLK length = 6 bytes.
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|   {}
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| }     // End _PR
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| 
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| 
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