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8a5782d704
Currently, "push byte %[Vector]" causes nasm warning when Vector is larger than 0x7F. This is because push accepts a signed value, and byte means signed int8. Maximum signed int8 is 0x7F. When Vector is larger the 0x7F, for example, when Vector is 255, byte 255 turns to -1, and causes the warning "signed byte value exceeds". To avoid such warning, use dword instead of byte, this will increase 3 bytes for each IdtVector. For IA32, the size of IdtVector will increase from 10 bytes to 13 bytes. For X64, the size of IdtVector will increase from 15 bytes to 18 bytes. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Harry Han <harry.han@intel.com> Cc: Catharine West <catharine.west@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
457 lines
12 KiB
NASM
457 lines
12 KiB
NASM
;------------------------------------------------------------------------------ ;
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; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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;
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; ExceptionHandlerAsm.Asm
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;
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; Abstract:
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;
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; IA32 CPU Exception Handler
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;
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; Notes:
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;
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;------------------------------------------------------------------------------
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;
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; CommonExceptionHandler()
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;
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extern ASM_PFX(CommonExceptionHandler)
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SECTION .data
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extern ASM_PFX(mErrorCodeFlag) ; Error code flags for exceptions
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extern ASM_PFX(mDoFarReturnFlag) ; Do far return flag
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SECTION .text
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ALIGN 8
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;
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; exception handler stub table
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;
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AsmIdtVectorBegin:
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%assign Vector 0
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%rep 256
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push strict dword %[Vector];
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push eax
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mov eax, ASM_PFX(CommonInterruptEntry)
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jmp eax
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%assign Vector Vector+1
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%endrep
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AsmIdtVectorEnd:
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HookAfterStubBegin:
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push strict dword 0 ; 0 will be fixed
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VectorNum:
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push eax
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mov eax, HookAfterStubHeaderEnd
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jmp eax
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HookAfterStubHeaderEnd:
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pop eax
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sub esp, 8 ; reserve room for filling exception data later
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push dword [esp + 8]
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xchg ecx, [esp] ; get vector number
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bt [ASM_PFX(mErrorCodeFlag)], ecx
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jnc .0
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push dword [esp] ; addition push if exception data needed
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.0:
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xchg ecx, [esp] ; restore ecx
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push eax
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;----------------------------------------------------------------------------;
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; CommonInterruptEntry ;
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;----------------------------------------------------------------------------;
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; The follow algorithm is used for the common interrupt routine.
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; Entry from each interrupt with a push eax and eax=interrupt number
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; Stack:
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; +---------------------+
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; + EFlags +
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; +---------------------+
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; + CS +
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; +---------------------+
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; + EIP +
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; +---------------------+
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; + Error Code +
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; +---------------------+
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; + Vector Number +
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; +---------------------+
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; + EBP +
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; +---------------------+ <-- EBP
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global ASM_PFX(CommonInterruptEntry)
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ASM_PFX(CommonInterruptEntry):
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cli
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pop eax
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;
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; All interrupt handlers are invoked through interrupt gates, so
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; IF flag automatically cleared at the entry point
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;
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;
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; Get vector number from top of stack
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;
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xchg ecx, [esp]
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and ecx, 0xFF ; Vector number should be less than 256
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cmp ecx, 32 ; Intel reserved vector for exceptions?
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jae NoErrorCode
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bt [ASM_PFX(mErrorCodeFlag)], ecx
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jc HasErrorCode
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NoErrorCode:
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;
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; Stack:
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; +---------------------+
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; + EFlags +
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; +---------------------+
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; + CS +
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; +---------------------+
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; + EIP +
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; +---------------------+
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; + ECX +
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; +---------------------+ <-- ESP
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;
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; Registers:
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; ECX - Vector Number
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;
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;
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; Put Vector Number on stack
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;
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push ecx
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;
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; Put 0 (dummy) error code on stack, and restore ECX
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;
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xor ecx, ecx ; ECX = 0
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xchg ecx, [esp+4]
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jmp ErrorCodeAndVectorOnStack
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HasErrorCode:
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;
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; Stack:
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; +---------------------+
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; + EFlags +
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; +---------------------+
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; + CS +
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; +---------------------+
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; + EIP +
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; +---------------------+
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; + Error Code +
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; +---------------------+
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; + ECX +
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; +---------------------+ <-- ESP
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;
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; Registers:
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; ECX - Vector Number
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;
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;
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; Put Vector Number on stack and restore ECX
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;
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xchg ecx, [esp]
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ErrorCodeAndVectorOnStack:
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push ebp
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mov ebp, esp
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;
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; Stack:
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; +---------------------+
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; + EFlags +
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; +---------------------+
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; + CS +
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; +---------------------+
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; + EIP +
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; +---------------------+
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; + Error Code +
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; +---------------------+
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; + Vector Number +
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; +---------------------+
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; + EBP +
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; +---------------------+ <-- EBP
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;
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;
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; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32
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; is 16-byte aligned
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;
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and esp, 0xfffffff0
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sub esp, 12
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sub esp, 8
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push 0 ; clear EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
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push 0 ; clear EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
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;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
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push eax
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push ecx
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push edx
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push ebx
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lea ecx, [ebp + 6 * 4]
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push ecx ; ESP
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push dword [ebp] ; EBP
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push esi
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push edi
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;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
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mov eax, ss
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push eax
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movzx eax, word [ebp + 4 * 4]
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push eax
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mov eax, ds
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push eax
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mov eax, es
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push eax
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mov eax, fs
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push eax
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mov eax, gs
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push eax
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;; UINT32 Eip;
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mov eax, [ebp + 3 * 4]
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push eax
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;; UINT32 Gdtr[2], Idtr[2];
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sub esp, 8
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sidt [esp]
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mov eax, [esp + 2]
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xchg eax, [esp]
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and eax, 0xFFFF
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mov [esp+4], eax
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sub esp, 8
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sgdt [esp]
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mov eax, [esp + 2]
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xchg eax, [esp]
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and eax, 0xFFFF
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mov [esp+4], eax
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;; UINT32 Ldtr, Tr;
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xor eax, eax
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str ax
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push eax
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sldt ax
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push eax
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;; UINT32 EFlags;
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mov eax, [ebp + 5 * 4]
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push eax
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;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
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mov eax, 1
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push ebx ; temporarily save value of ebx on stack
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cpuid ; use CPUID to determine if FXSAVE/FXRESTOR and DE
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; are supported
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pop ebx ; retore value of ebx that was overwritten by CPUID
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mov eax, cr4
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push eax ; push cr4 firstly
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test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
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jz .1
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or eax, BIT9 ; Set CR4.OSFXSR
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.1:
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test edx, BIT2 ; Test for Debugging Extensions support
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jz .2
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or eax, BIT3 ; Set CR4.DE
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.2:
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mov cr4, eax
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mov eax, cr3
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push eax
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mov eax, cr2
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push eax
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xor eax, eax
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push eax
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mov eax, cr0
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push eax
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;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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mov eax, dr7
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push eax
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mov eax, dr6
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push eax
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mov eax, dr3
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push eax
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mov eax, dr2
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push eax
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mov eax, dr1
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push eax
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mov eax, dr0
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push eax
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;; FX_SAVE_STATE_IA32 FxSaveState;
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sub esp, 512
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mov edi, esp
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test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.
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; edx still contains result from CPUID above
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jz .3
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fxsave [edi]
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.3:
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;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
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cld
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;; UINT32 ExceptionData;
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push dword [ebp + 2 * 4]
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;; Prepare parameter and call
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mov edx, esp
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push edx
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mov edx, dword [ebp + 1 * 4]
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push edx
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;
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; Call External Exception Handler
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;
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mov eax, ASM_PFX(CommonExceptionHandler)
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call eax
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add esp, 8
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cli
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;; UINT32 ExceptionData;
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add esp, 4
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;; FX_SAVE_STATE_IA32 FxSaveState;
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mov esi, esp
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mov eax, 1
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cpuid ; use CPUID to determine if FXSAVE/FXRESTOR
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; are supported
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test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
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jz .4
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fxrstor [esi]
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.4:
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add esp, 512
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;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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;; Skip restoration of DRx registers to support in-circuit emualators
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;; or debuggers set breakpoint in interrupt/exception context
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add esp, 4 * 6
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;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
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pop eax
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mov cr0, eax
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add esp, 4 ; not for Cr1
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pop eax
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mov cr2, eax
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pop eax
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mov cr3, eax
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pop eax
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mov cr4, eax
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;; UINT32 EFlags;
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pop dword [ebp + 5 * 4]
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;; UINT32 Ldtr, Tr;
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;; UINT32 Gdtr[2], Idtr[2];
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;; Best not let anyone mess with these particular registers...
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add esp, 24
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;; UINT32 Eip;
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pop dword [ebp + 3 * 4]
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;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
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;; NOTE - modified segment registers could hang the debugger... We
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;; could attempt to insulate ourselves against this possibility,
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;; but that poses risks as well.
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;;
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pop gs
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pop fs
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pop es
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pop ds
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pop dword [ebp + 4 * 4]
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pop ss
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;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
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pop edi
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pop esi
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add esp, 4 ; not for ebp
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add esp, 4 ; not for esp
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pop ebx
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pop edx
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pop ecx
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pop eax
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pop dword [ebp - 8]
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pop dword [ebp - 4]
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mov esp, ebp
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pop ebp
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add esp, 8
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cmp dword [esp - 16], 0 ; check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
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jz DoReturn
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cmp dword [esp - 20], 1 ; check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
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jz ErrorCode
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jmp dword [esp - 16]
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ErrorCode:
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sub esp, 4
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jmp dword [esp - 12]
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DoReturn:
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cmp dword [ASM_PFX(mDoFarReturnFlag)], 0 ; Check if need to do far return instead of IRET
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jz DoIret
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push dword [esp + 8] ; save EFLAGS
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add esp, 16
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push dword [esp - 8] ; save CS in new location
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push dword [esp - 8] ; save EIP in new location
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push dword [esp - 8] ; save EFLAGS in new location
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popfd ; restore EFLAGS
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retf ; far return
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DoIret:
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iretd
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;---------------------------------------;
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; _AsmGetTemplateAddressMap ;
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;----------------------------------------------------------------------------;
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;
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; Protocol prototype
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; AsmGetTemplateAddressMap (
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; EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
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; );
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;
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; Routine Description:
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;
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; Return address map of interrupt handler template so that C code can generate
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; interrupt table.
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;
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; Arguments:
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;
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;
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; Returns:
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;
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; Nothing
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;
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;
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; Input: [ebp][0] = Original ebp
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; [ebp][4] = Return address
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;
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; Output: Nothing
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;
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; Destroys: Nothing
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;-----------------------------------------------------------------------------;
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global ASM_PFX(AsmGetTemplateAddressMap)
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ASM_PFX(AsmGetTemplateAddressMap):
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push ebp ; C prolog
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mov ebp, esp
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pushad
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mov ebx, dword [ebp + 0x8]
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mov dword [ebx], AsmIdtVectorBegin
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mov dword [ebx + 0x4], (AsmIdtVectorEnd - AsmIdtVectorBegin) / 256
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mov dword [ebx + 0x8], HookAfterStubBegin
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popad
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pop ebp
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ret
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;-------------------------------------------------------------------------------------
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; AsmVectorNumFixup (*NewVectorAddr, VectorNum, *OldVectorAddr);
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;-------------------------------------------------------------------------------------
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global ASM_PFX(AsmVectorNumFixup)
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ASM_PFX(AsmVectorNumFixup):
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mov eax, dword [esp + 8]
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mov ecx, [esp + 4]
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mov [ecx + (VectorNum - 4 - HookAfterStubBegin)], al
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ret
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