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257 lines
8.9 KiB
Groff
257 lines
8.9 KiB
Groff
.\" DO NOT MODIFY THIS FILE! It was generated by help2man 1.41.2.
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.TH LLVM "1" "June 2013" "LLVM (http://llvm.org/):" "User Commands"
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.SH NAME
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LLVM \- manual page for LLVM (http://llvm.org/):
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.SH DESCRIPTION
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USAGE: cpp11\-migrate [options] <source0> [... <sourceN>]
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.SS "OPTIONS:"
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.HP
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\fB\-add\-override\fR \- Make use of override specifier where possible
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.HP
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\fB\-asm\-verbose\fR \- Add comments to directives.
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.HP
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\fB\-bounds\-checking\-single\-trap\fR \- Use one trap block per function
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.HP
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\fB\-cppfname=\fR<function name> \- Specify the name of the generated function
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.HP
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\fB\-cppfor=\fR<string> \- Specify the name of the thing to generate
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.HP
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\fB\-cppgen\fR \- Choose what kind of output to generate
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.TP
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=program
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\- Generate a complete program
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.TP
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=module
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\- Generate a module definition
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.TP
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=contents
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\- Generate contents of a module
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.TP
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=function
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\- Generate a function definition
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.TP
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=functions
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\- Generate all function definitions
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.TP
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=inline
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\- Generate an inline function
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.TP
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=variable
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\- Generate a variable definition
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.TP
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=type
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\- Generate a type definition
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.HP
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\fB\-disable\-spill\-fusing\fR \- Disable fusing of spill code into instructions
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.IP
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Choose driver interface:
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.HP
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\fB\-drvnvcl\fR \- Nvidia OpenCL driver
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.HP
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\fB\-drvcuda\fR \- Nvidia CUDA driver
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.HP
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\fB\-drvtest\fR \- Plain Test
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.HP
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\fB\-enable\-correct\-eh\-support\fR \- Make the \fB\-lowerinvoke\fR pass insert expensive, but correct, EH code
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.HP
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\fB\-enable\-load\-pre\fR \-
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.HP
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\fB\-enable\-objc\-arc\-opts\fR \- enable/disable all ARC Optimizations
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.HP
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\fB\-enable\-tbaa\fR \-
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.HP
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\fB\-fatal\-assembler\-warnings\fR \- Consider warnings as error
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.HP
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\fB\-fdata\-sections\fR \- Emit data into separate sections
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.HP
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\fB\-ffunction\-sections\fR \- Emit functions into separate sections
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.HP
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\fB\-final\-syntax\-check\fR \- Check for correct syntax after applying transformations
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.HP
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\fB\-help\fR \- Display available options (\fB\-help\-hidden\fR for more)
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.HP
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\fB\-internalize\-public\-api\-file=\fR<filename> \- A file containing list of symbol names to preserve
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.HP
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\fB\-internalize\-public\-api\-list=\fR<list> \- A list of symbol names to preserve
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.HP
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\fB\-join\-liveintervals\fR \- Coalesce copies (default=true)
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.HP
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\fB\-limit\-float\-precision=\fR<uint> \- Generate low\-precision inline sequences for some float libcalls
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.HP
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\fB\-loop\-convert\fR \- Make use of range\-based for loops where possible
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.HP
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\fB\-mc\-x86\-disable\-arith\-relaxation\fR \- Disable relaxation of arithmetic instruction for X86
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.HP
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\fB\-mips16\-hard\-float\fR \- MIPS: mips16 hard float enable.
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.HP
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\fB\-msp430\-hwmult\-mode\fR \- Hardware multiplier use mode
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.TP
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=no
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\- Do not use hardware multiplier
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.TP
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=interrupts
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\- Assume hardware multiplier can be used inside interrupts
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.TP
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=use
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\- Assume hardware multiplier cannot be used inside interrupts
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.HP
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\fB\-nvptx\-emit\-line\-numbers\fR \- NVPTX Specific: Emit Line numbers even without \fB\-G\fR
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.HP
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\fB\-nvptx\-emit\-src\fR \- NVPTX Specific: Emit source line in ptx file
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.TP
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\fB\-nvptx\-fma\-level=\fR<int> \- NVPTX Specific: FMA contraction (0: don't do it 1: do it
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2: do it aggressively
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.HP
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\fB\-nvptx\-mad\-enable\fR \- NVPTX Specific: Enable generating FMAD instructions
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.HP
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\fB\-nvptx\-prec\-divf32=\fR<int> \- NVPTX Specifies: 0 use div.approx, 1 use div.full, 2 use IEEE Compliant F32 div.rnd if avaiable.
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.HP
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\fB\-nvptx\-sched4reg\fR \- NVPTX Specific: schedule for register pressue
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.HP
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\fB\-nvvm\-reflect\-enable\fR \- NVVM reflection, enabled by default
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.HP
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\fB\-nvvm\-reflect\-list=\fR<name=<int>> \- A list of string=num assignments
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.HP
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\fB\-p=\fR<string> \- Build path
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.HP
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\fB\-pre\-RA\-sched\fR \- Instruction schedulers available (before register allocation):
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.TP
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=vliw\-td
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\- VLIW scheduler
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.TP
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=list\-ilp
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\- Bottom\-up register pressure aware list scheduling which tries to balance ILP and register pressure
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.TP
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=list\-hybrid
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\- Bottom\-up register pressure aware list scheduling which tries to balance latency and register pressure
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.TP
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=source
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\- Similar to list\-burr but schedules in source order when possible
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.TP
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=list\-burr
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\- Bottom\-up register reduction list scheduling
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.TP
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=linearize
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\- Linearize DAG, no scheduling
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.TP
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=fast
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\- Fast suboptimal list scheduling
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.TP
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=default
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\- Best scheduler for the target
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.HP
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\fB\-print\-after\-all\fR \- Print IR after each pass
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.HP
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\fB\-print\-before\-all\fR \- Print IR before each pass
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.HP
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\fB\-print\-machineinstrs=\fR<pass\-name> \- Print machine instrs
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.HP
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\fB\-profile\-estimator\-loop\-weight=\fR<loop\-weight> \- Number of loop executions used for profile\-estimator
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.HP
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\fB\-profile\-file=\fR<filename> \- Profile file loaded by \fB\-profile\-metadata\-loader\fR
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.HP
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\fB\-profile\-info\-file=\fR<filename> \- Profile file loaded by \fB\-profile\-loader\fR
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.HP
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\fB\-profile\-verifier\-noassert\fR \- Disable assertions
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.HP
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\fB\-regalloc\fR \- Register allocator to use
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.TP
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=default
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\- pick register allocator based on \fB\-O\fR option
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.TP
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=basic
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\- basic register allocator
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.TP
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=fast
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\- fast register allocator
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.TP
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=greedy
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\- greedy register allocator
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.TP
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=pbqp
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\- PBQP register allocator
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.HP
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\fB\-risk\fR \- Select a maximum risk level:
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.TP
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=safe
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\- Only safe transformations
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.TP
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=reasonable
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\- Enable transformations that might change semantics (default)
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.TP
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=risky
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\- Enable transformations that are likely to change semantics
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.HP
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\fB\-shrink\-wrap\fR \- Shrink wrap callee\-saved register spills/restores
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.HP
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\fB\-spiller\fR \- Spiller to use: (default: standard)
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.TP
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=trivial
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\- trivial spiller
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.TP
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=inline
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\- inline spiller
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.HP
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\fB\-stats\fR \- Enable statistics output from program (available with Asserts)
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.HP
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\fB\-struct\-path\-tbaa\fR \-
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.HP
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\fB\-summary\fR \- Print transform summary
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.HP
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\fB\-time\-passes\fR \- Time each pass, printing elapsed time for each on exit
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.HP
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\fB\-use\-auto\fR \- Use of 'auto' type specifier
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.HP
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\fB\-use\-nullptr\fR \- Make use of nullptr keyword where possible
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.HP
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\fB\-user\-null\-macros=\fR<string> \- Comma\-separated list of user\-defined macro names that behave like NULL
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.HP
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\fB\-vectorize\-loops\fR \- Run the Loop vectorization passes
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.HP
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\fB\-vectorize\-slp\fR \- Run the SLP vectorization passes
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.HP
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\fB\-vectorize\-slp\-aggressive\fR \- Run the BB vectorization passes
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.HP
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\fB\-verify\-dom\-info\fR \- Verify dominator info (time consuming)
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.HP
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\fB\-verify\-loop\-info\fR \- Verify loop info (time consuming)
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.HP
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\fB\-verify\-regalloc\fR \- Verify during register allocation
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.HP
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\fB\-verify\-region\-info\fR \- Verify region info (time consuming)
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.HP
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\fB\-verify\-scev\fR \- Verify ScalarEvolution's backedge taken counts (slow)
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.HP
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\fB\-version\fR \- Display the version of this program
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.HP
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\fB\-x86\-asm\-syntax\fR \- Choose style of code to emit from X86 backend:
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.TP
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=att
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\- Emit AT&T\-style assembly
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.TP
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=intel
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\- Emit Intel\-style assembly
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.HP
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\fB\-x86\-early\-ifcvt\fR \- Enable early if\-conversion on X86
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.HP
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\fB\-x86\-use\-vzeroupper\fR \- Minimize AVX to SSE transition penalty
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.IP
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LLVM version 3.3
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.IP
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Optimized build.
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Built May 7 2013 (21:07:59).
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Default target: x86_64\-pc\-linux\-gnu
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Host CPU: corei7\-avx
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.SH "SEE ALSO"
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The full documentation for
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.B LLVM
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is maintained as a Texinfo manual. If the
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.B info
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and
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.B LLVM
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programs are properly installed at your site, the command
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.IP
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.B info LLVM
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.PP
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should give you access to the complete manual.
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