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https://git.proxmox.com/git/llvm-toolchain
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218 lines
8.2 KiB
Diff
218 lines
8.2 KiB
Diff
From f970b007e55d6dab6d84d98a39658a58019eb06e Mon Sep 17 00:00:00 2001
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From: David Green <david.green@arm.com>
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Date: Wed, 2 Nov 2022 22:34:05 +0000
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Subject: [PATCH] [ARM] Fix vector ule zero lowering
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The instruction icmp ule <4 x i32> %0, zeroinitializer will usually be
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simplified to icmp eq <4 x i32> %0, zeroinitializer. It is not
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guaranteed though, and the code for lowering vector compares could pick
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the wrong form of the instruction if this happened. I've tried to make
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the code more explicit about the supported conditions.
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This fixes NEON being unable to select VCMPZ with HS conditions, and
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fixes some incorrect MVE patterns.
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Fixes #58514.
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Differential Revision: https://reviews.llvm.org/D136447
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---
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llvm/lib/Target/ARM/ARMISelLowering.cpp | 18 +++++++-------
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llvm/test/CodeGen/ARM/vcmpz.ll | 30 ++++++++++++++++--------
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llvm/test/CodeGen/Thumb2/mve-pred-and.ll | 3 ++-
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llvm/test/CodeGen/Thumb2/mve-pred-or.ll | 3 ++-
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llvm/test/CodeGen/Thumb2/mve-pred-xor.ll | 3 ++-
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llvm/test/CodeGen/Thumb2/mve-vcmpz.ll | 18 +++++++++-----
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6 files changed, 47 insertions(+), 28 deletions(-)
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diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
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index c84fe4d66197..b822f15ed193 100644
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--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
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+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
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@@ -6829,25 +6829,25 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG,
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// If one of the operands is a constant vector zero, attempt to fold the
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// comparison to a specialized compare-against-zero form.
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- SDValue SingleOp;
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- if (ISD::isBuildVectorAllZeros(Op1.getNode()))
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- SingleOp = Op0;
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- else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
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+ if (ISD::isBuildVectorAllZeros(Op0.getNode()) &&
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+ (Opc == ARMCC::GE || Opc == ARMCC::GT || Opc == ARMCC::EQ ||
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+ Opc == ARMCC::NE)) {
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if (Opc == ARMCC::GE)
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Opc = ARMCC::LE;
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else if (Opc == ARMCC::GT)
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Opc = ARMCC::LT;
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- SingleOp = Op1;
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+ std::swap(Op0, Op1);
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}
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SDValue Result;
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- if (SingleOp.getNode()) {
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- Result = DAG.getNode(ARMISD::VCMPZ, dl, CmpVT, SingleOp,
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+ if (ISD::isBuildVectorAllZeros(Op1.getNode()) &&
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+ (Opc == ARMCC::GE || Opc == ARMCC::GT || Opc == ARMCC::LE ||
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+ Opc == ARMCC::LT || Opc == ARMCC::NE || Opc == ARMCC::EQ))
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+ Result = DAG.getNode(ARMISD::VCMPZ, dl, CmpVT, Op0,
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DAG.getConstant(Opc, dl, MVT::i32));
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- } else {
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+ else
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Result = DAG.getNode(ARMISD::VCMP, dl, CmpVT, Op0, Op1,
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DAG.getConstant(Opc, dl, MVT::i32));
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- }
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Result = DAG.getSExtOrTrunc(Result, dl, VT);
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diff --git a/llvm/test/CodeGen/ARM/vcmpz.ll b/llvm/test/CodeGen/ARM/vcmpz.ll
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index f800346a6b56..51b5d28d8192 100644
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--- a/llvm/test/CodeGen/ARM/vcmpz.ll
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+++ b/llvm/test/CodeGen/ARM/vcmpz.ll
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@@ -174,11 +174,16 @@ define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_ult(<4 x i32> %0) {
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ret <4 x i32> %3
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}
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-;define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_ule(<4 x i32> %0) {
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-; %2 = icmp ule <4 x i32> %0, zeroinitializer
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-; %3 = sext <4 x i1> %2 to <4 x i32>
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-; ret <4 x i32> %3
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-;}
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+define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_ule(<4 x i32> %0) {
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+; CHECK-LABEL: vcmpz_zr_ule:
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+; CHECK: @ %bb.0:
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+; CHECK-NEXT: vmov.i32 q8, #0x0
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+; CHECK-NEXT: vcge.u32 q0, q8, q0
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+; CHECK-NEXT: bx lr
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+ %2 = icmp ule <4 x i32> %0, zeroinitializer
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+ %3 = sext <4 x i1> %2 to <4 x i32>
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+ ret <4 x i32> %3
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+}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_ugt(<4 x i32> %0) {
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; CHECK-LABEL: vcmpz_zr_ugt:
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@@ -294,8 +299,13 @@ define arm_aapcs_vfpcc <4 x i32> @vcmpz_zl_ugt(<4 x i32> %0) {
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ret <4 x i32> %3
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}
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-;define arm_aapcs_vfpcc <4 x i32> @vcmpz_zl_uge(<4 x i32> %0) {
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-; %2 = icmp uge <4 x i32> zeroinitializer, %0
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-; %3 = sext <4 x i1> %2 to <4 x i32>
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-; ret <4 x i32> %3
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-;}
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+define arm_aapcs_vfpcc <4 x i32> @vcmpz_zl_uge(<4 x i32> %0) {
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+; CHECK-LABEL: vcmpz_zl_uge:
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+; CHECK: @ %bb.0:
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+; CHECK-NEXT: vmov.i32 q8, #0x0
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+; CHECK-NEXT: vcge.u32 q0, q8, q0
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+; CHECK-NEXT: bx lr
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+ %2 = icmp uge <4 x i32> zeroinitializer, %0
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+ %3 = sext <4 x i1> %2 to <4 x i32>
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+ ret <4 x i32> %3
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+}
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diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-and.ll b/llvm/test/CodeGen/Thumb2/mve-pred-and.ll
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index e745fafdbea7..e8d5eadabf7f 100644
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--- a/llvm/test/CodeGen/Thumb2/mve-pred-and.ll
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+++ b/llvm/test/CodeGen/Thumb2/mve-pred-and.ll
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@@ -122,8 +122,9 @@ entry:
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define arm_aapcs_vfpcc <4 x i32> @cmpulez_v4i1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: cmpulez_v4i1:
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; CHECK: @ %bb.0: @ %entry
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+; CHECK-NEXT: vmov.i32 q2, #0x0
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; CHECK-NEXT: vpt.i32 eq, q0, zr
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-; CHECK-NEXT: vcmpt.u32 cs, q1, zr
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+; CHECK-NEXT: vcmpt.u32 cs, q2, q1
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-or.ll b/llvm/test/CodeGen/Thumb2/mve-pred-or.ll
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index cb3f554e21b0..435ddf0a6e57 100644
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--- a/llvm/test/CodeGen/Thumb2/mve-pred-or.ll
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+++ b/llvm/test/CodeGen/Thumb2/mve-pred-or.ll
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@@ -123,7 +123,8 @@ entry:
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define arm_aapcs_vfpcc <4 x i32> @cmpulez_v4i1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: cmpulez_v4i1:
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; CHECK: @ %bb.0: @ %entry
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-; CHECK-NEXT: vcmp.u32 cs, q1, zr
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+; CHECK-NEXT: vmov.i32 q2, #0x0
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+; CHECK-NEXT: vcmp.u32 cs, q2, q1
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; CHECK-NEXT: vpnot
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vcmpt.i32 ne, q0, zr
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diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-xor.ll b/llvm/test/CodeGen/Thumb2/mve-pred-xor.ll
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index e5fef332034f..0ff262e6b53a 100644
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--- a/llvm/test/CodeGen/Thumb2/mve-pred-xor.ll
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+++ b/llvm/test/CodeGen/Thumb2/mve-pred-xor.ll
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@@ -151,7 +151,8 @@ entry:
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define arm_aapcs_vfpcc <4 x i32> @cmpulez_v4i1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: cmpulez_v4i1:
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; CHECK: @ %bb.0: @ %entry
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-; CHECK-NEXT: vcmp.u32 cs, q1, zr
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+; CHECK-NEXT: vmov.i32 q2, #0x0
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+; CHECK-NEXT: vcmp.u32 cs, q2, q1
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; CHECK-NEXT: vmrs r0, p0
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; CHECK-NEXT: vcmp.i32 eq, q0, zr
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; CHECK-NEXT: vmrs r1, p0
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diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpz.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpz.ll
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index fcb9d136307f..aaf49c76a07a 100644
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--- a/llvm/test/CodeGen/Thumb2/mve-vcmpz.ll
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+++ b/llvm/test/CodeGen/Thumb2/mve-vcmpz.ll
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@@ -110,7 +110,8 @@ entry:
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define arm_aapcs_vfpcc <4 x i32> @vcmp_ulez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: vcmp_ulez_v4i32:
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; CHECK: @ %bb.0: @ %entry
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-; CHECK-NEXT: vcmp.u32 cs, q0, zr
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+; CHECK-NEXT: vmov.i32 q3, #0x0
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+; CHECK-NEXT: vcmp.u32 cs, q3, q0
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; CHECK-NEXT: vpsel q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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@@ -229,7 +230,8 @@ entry:
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define arm_aapcs_vfpcc <8 x i16> @vcmp_ulez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: vcmp_ulez_v8i16:
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; CHECK: @ %bb.0: @ %entry
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-; CHECK-NEXT: vcmp.u16 cs, q0, zr
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+; CHECK-NEXT: vmov.i32 q3, #0x0
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+; CHECK-NEXT: vcmp.u16 cs, q3, q0
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; CHECK-NEXT: vpsel q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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@@ -348,7 +350,8 @@ entry:
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define arm_aapcs_vfpcc <16 x i8> @vcmp_ulez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: vcmp_ulez_v16i8:
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; CHECK: @ %bb.0: @ %entry
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-; CHECK-NEXT: vcmp.u8 cs, q0, zr
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+; CHECK-NEXT: vmov.i32 q3, #0x0
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+; CHECK-NEXT: vcmp.u8 cs, q3, q0
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; CHECK-NEXT: vpsel q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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@@ -489,7 +492,8 @@ entry:
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define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ugez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: vcmp_r_ugez_v4i32:
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; CHECK: @ %bb.0: @ %entry
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-; CHECK-NEXT: vcmp.u32 cs, q0, zr
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+; CHECK-NEXT: vmov.i32 q3, #0x0
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+; CHECK-NEXT: vcmp.u32 cs, q3, q0
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; CHECK-NEXT: vpsel q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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@@ -608,7 +612,8 @@ entry:
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define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ugez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: vcmp_r_ugez_v8i16:
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; CHECK: @ %bb.0: @ %entry
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-; CHECK-NEXT: vcmp.u16 cs, q0, zr
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+; CHECK-NEXT: vmov.i32 q3, #0x0
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+; CHECK-NEXT: vcmp.u16 cs, q3, q0
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; CHECK-NEXT: vpsel q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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@@ -727,7 +732,8 @@ entry:
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define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ugez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: vcmp_r_ugez_v16i8:
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; CHECK: @ %bb.0: @ %entry
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-; CHECK-NEXT: vcmp.u8 cs, q0, zr
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+; CHECK-NEXT: vmov.i32 q3, #0x0
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+; CHECK-NEXT: vcmp.u8 cs, q3, q0
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; CHECK-NEXT: vpsel q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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