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138 lines
6.9 KiB
Diff
138 lines
6.9 KiB
Diff
Description: PowerPC/SPE: Fix register spilling for SPE registers
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Author: Justin Hibbits <jrh29@alumni.cwru.edu>
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Origin: https://reviews.llvm.org/D56703
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Last-Update: 2019-02-14
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--- llvm-toolchain-snapshot-9~svn351420.orig/lib/Target/PowerPC/PPCCallingConv.td
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+++ llvm-toolchain-snapshot-9~svn351420/lib/Target/PowerPC/PPCCallingConv.td
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@@ -346,15 +346,22 @@ def CSR_NoRegs : CalleeSavedRegs<(add)>;
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// and value may be altered by inter-library calls.
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// Do not include r12 as it is used as a scratch register.
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// Do not include return registers r3, f1, v2.
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-def CSR_SVR32_ColdCC : CalleeSavedRegs<(add (sequence "R%u", 4, 10),
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- (sequence "R%u", 14, 31),
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- F0, (sequence "F%u", 2, 31),
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- (sequence "CR%u", 0, 7))>;
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+def CSR_SVR32_ColdCC_Common : CalleeSavedRegs<(add (sequence "R%u", 4, 10),
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+ (sequence "R%u", 14, 31),
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+ (sequence "CR%u", 0, 7))>;
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+
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+def CSR_SVR32_ColdCC : CalleeSavedRegs<(add CSR_SVR32_ColdCC_Common,
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+ F0, (sequence "F%u", 2, 31))>;
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+
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def CSR_SVR32_ColdCC_Altivec : CalleeSavedRegs<(add CSR_SVR32_ColdCC,
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(sequence "V%u", 0, 1),
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(sequence "V%u", 3, 31))>;
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+def CSR_SVR32_ColdCC_SPE : CalleeSavedRegs<(add CSR_SVR32_ColdCC_Common,
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+ (sequence "S%u", 4, 10),
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+ (sequence "S%u", 14, 31))>;
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+
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def CSR_SVR64_ColdCC : CalleeSavedRegs<(add (sequence "X%u", 4, 10),
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(sequence "X%u", 14, 31),
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F0, (sequence "F%u", 2, 31),
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--- llvm-toolchain-snapshot-9~svn351420.orig/lib/Target/PowerPC/PPCInstrInfo.cpp
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+++ llvm-toolchain-snapshot-9~svn351420/lib/Target/PowerPC/PPCInstrInfo.cpp
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@@ -996,6 +996,8 @@ void PPCInstrInfo::copyPhysReg(MachineBa
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Opc = PPC::QVFMRb;
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else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
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Opc = PPC::CROR;
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+ else if (PPC::SPE4RCRegClass.contains(DestReg, SrcReg))
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+ Opc = PPC::OR;
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else if (PPC::SPERCRegClass.contains(DestReg, SrcReg))
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Opc = PPC::EVOR;
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else
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@@ -1026,10 +1028,10 @@ unsigned PPCInstrInfo::getStoreOpcodeFor
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OpcodeIndex = SOK_Float8Spill;
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} else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
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OpcodeIndex = SOK_Float4Spill;
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- } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
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- OpcodeIndex = SOK_SPESpill;
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} else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
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OpcodeIndex = SOK_SPE4Spill;
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+ } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
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+ OpcodeIndex = SOK_SPESpill;
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} else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
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OpcodeIndex = SOK_CRSpill;
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} else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
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@@ -1066,6 +1068,10 @@ unsigned PPCInstrInfo::getStoreOpcodeFor
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OpcodeIndex = SOK_Float8Spill;
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} else if (PPC::F4RCRegClass.contains(Reg)) {
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OpcodeIndex = SOK_Float4Spill;
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+ } else if (PPC::SPE4RCRegClass.contains(Reg)) {
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+ OpcodeIndex = SOK_SPE4Spill;
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+ } else if (PPC::SPERCRegClass.contains(Reg)) {
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+ OpcodeIndex = SOK_SPESpill;
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} else if (PPC::CRRCRegClass.contains(Reg)) {
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OpcodeIndex = SOK_CRSpill;
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} else if (PPC::CRBITRCRegClass.contains(Reg)) {
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@@ -1112,10 +1118,10 @@ PPCInstrInfo::getLoadOpcodeForSpill(unsi
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OpcodeIndex = SOK_Float8Spill;
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} else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
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OpcodeIndex = SOK_Float4Spill;
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- } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
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- OpcodeIndex = SOK_SPESpill;
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} else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
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OpcodeIndex = SOK_SPE4Spill;
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+ } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
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+ OpcodeIndex = SOK_SPESpill;
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} else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
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OpcodeIndex = SOK_CRSpill;
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} else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
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@@ -1152,6 +1158,10 @@ PPCInstrInfo::getLoadOpcodeForSpill(unsi
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OpcodeIndex = SOK_Float8Spill;
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} else if (PPC::F4RCRegClass.contains(Reg)) {
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OpcodeIndex = SOK_Float4Spill;
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+ } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
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+ OpcodeIndex = SOK_SPE4Spill;
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+ } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
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+ OpcodeIndex = SOK_SPESpill;
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} else if (PPC::CRRCRegClass.contains(Reg)) {
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OpcodeIndex = SOK_CRSpill;
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} else if (PPC::CRBITRCRegClass.contains(Reg)) {
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--- llvm-toolchain-snapshot-9~svn351420.orig/lib/Target/PowerPC/PPCRegisterInfo.cpp
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+++ llvm-toolchain-snapshot-9~svn351420/lib/Target/PowerPC/PPCRegisterInfo.cpp
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@@ -167,7 +167,9 @@ PPCRegisterInfo::getCalleeSavedRegs(cons
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: (SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList
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: CSR_SVR64_ColdCC_SaveList))
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: (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_SaveList
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- : CSR_SVR32_ColdCC_SaveList);
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+ : (Subtarget.hasSPE()
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+ ? CSR_SVR32_ColdCC_SPE_SaveList
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+ : CSR_SVR32_ColdCC_SaveList));
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}
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return TM.isPPC64()
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@@ -176,7 +178,9 @@ PPCRegisterInfo::getCalleeSavedRegs(cons
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: CSR_SVR464_Altivec_SaveList)
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: (SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList))
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: (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList
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- : CSR_SVR432_SaveList);
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+ : (Subtarget.hasSPE()
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+ ? CSR_SVR432_SPE_SaveList
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+ : CSR_SVR432_SaveList));
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}
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const MCPhysReg *
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@@ -226,13 +230,17 @@ PPCRegisterInfo::getCallPreservedMask(co
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return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask
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: CSR_SVR64_ColdCC_RegMask)
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: (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_RegMask
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- : CSR_SVR32_ColdCC_RegMask);
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+ : (Subtarget.hasSPE()
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+ ? CSR_SVR32_ColdCC_SPE_RegMask
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+ : CSR_SVR32_ColdCC_RegMask));
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}
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return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask
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: CSR_SVR464_RegMask)
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: (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask
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- : CSR_SVR432_RegMask);
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+ : (Subtarget.hasSPE()
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+ ? CSR_SVR432_SPE_RegMask
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+ : CSR_SVR432_RegMask));
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}
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const uint32_t*
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