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fdacc67577
* Add support for riscv64:
- Always link with -latomic on riscv64.
- patches/clang-riscv64-multiarch.diff: add multiarch paths for riscv64.
- patches/clang-riscv64-rv64gc.diff: default to lp64d ABI and rv64gc ISA.
- patches/clang-riscv64-hf-abi.diff: backport riscv64 hard-float support
from upstream.
- patches/libcxx/libcxx-riscv64-cycletimer.diff: backport riscv64
cycletimer support from upstream.
82 lines
3.1 KiB
Diff
82 lines
3.1 KiB
Diff
commit 09e6304440c08fe72b6ac05f922ab9d8b7f1e387
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Author: Roger Ferrer Ibanez <rofirrim@gmail.com>
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Date: Wed Jul 24 05:33:46 2019 +0000
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[RISCV] Implement benchmark::cycleclock::Now
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This is a cherrypick of D64237 onto llvm/utils/benchmark and
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libcxx/utils/google-benchmark.
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Differential Revision: https://reviews.llvm.org/D65142
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llvm-svn: 366868
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--- a/libcxx/utils/google-benchmark/README.LLVM
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+++ b/libcxx/utils/google-benchmark/README.LLVM
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@@ -4,3 +4,9 @@ LLVM notes
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This directory contains the Google Benchmark source code with some unnecessary
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files removed. Note that this directory is under a different license than
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libc++.
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+
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+Changes:
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+* https://github.com/google/benchmark/commit/4abdfbb802d1b514703223f5f852ce4a507d32d2
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+ is applied on top of
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+ https://github.com/google/benchmark/commit/4528c76b718acc9b57956f63069c699ae21edcab
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+ to add RISC-V timer support.
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--- a/libcxx/utils/google-benchmark/src/cycleclock.h
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+++ b/libcxx/utils/google-benchmark/src/cycleclock.h
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@@ -164,6 +164,21 @@ inline BENCHMARK_ALWAYS_INLINE int64_t Now() {
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uint64_t tsc;
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asm("stck %0" : "=Q"(tsc) : : "cc");
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return tsc;
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+#elif defined(__riscv) // RISC-V
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+ // Use RDCYCLE (and RDCYCLEH on riscv32)
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+#if __riscv_xlen == 32
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+ uint64_t cycles_low, cycles_hi0, cycles_hi1;
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+ asm("rdcycleh %0" : "=r"(cycles_hi0));
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+ asm("rdcycle %0" : "=r"(cycles_lo));
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+ asm("rdcycleh %0" : "=r"(cycles_hi1));
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+ // This matches the PowerPC overflow detection, above
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+ cycles_lo &= -static_cast<int64_t>(cycles_hi0 == cycles_hi1);
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+ return (cycles_hi1 << 32) | cycles_lo;
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+#else
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+ uint64_t cycles;
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+ asm("rdcycle %0" : "=r"(cycles));
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+ return cycles;
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+#endif
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#else
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// The soft failover to a generic implementation is automatic only for ARM.
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// For other platforms the developer is expected to make an attempt to create
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--- a/utils/benchmark/README.LLVM
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+++ b/utils/benchmark/README.LLVM
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@@ -23,3 +23,5 @@ Changes:
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is applied to disable exceptions in Microsoft STL when exceptions are disabled
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* Disabled CMake get_git_version as it is meaningless for this in-tree build,
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and hardcoded a null version
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+* https://github.com/google/benchmark/commit/4abdfbb802d1b514703223f5f852ce4a507d32d2
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+ is applied on top of v1.4.1 to add RISC-V timer support.
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--- a/utils/benchmark/src/cycleclock.h
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+++ b/utils/benchmark/src/cycleclock.h
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@@ -164,6 +164,21 @@ inline BENCHMARK_ALWAYS_INLINE int64_t Now() {
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uint64_t tsc;
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asm("stck %0" : "=Q" (tsc) : : "cc");
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return tsc;
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+#elif defined(__riscv) // RISC-V
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+ // Use RDCYCLE (and RDCYCLEH on riscv32)
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+#if __riscv_xlen == 32
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+ uint64_t cycles_low, cycles_hi0, cycles_hi1;
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+ asm("rdcycleh %0" : "=r"(cycles_hi0));
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+ asm("rdcycle %0" : "=r"(cycles_lo));
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+ asm("rdcycleh %0" : "=r"(cycles_hi1));
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+ // This matches the PowerPC overflow detection, above
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+ cycles_lo &= -static_cast<int64_t>(cycles_hi0 == cycles_hi1);
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+ return (cycles_hi1 << 32) | cycles_lo;
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+#else
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+ uint64_t cycles;
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+ asm("rdcycle %0" : "=r"(cycles));
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+ return cycles;
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+#endif
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#else
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// The soft failover to a generic implementation is automatic only for ARM.
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// For other platforms the developer is expected to make an attempt to create
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