mirror of
https://git.proxmox.com/git/llvm-toolchain
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93 lines
4.1 KiB
Diff
93 lines
4.1 KiB
Diff
The MIPS port aims to support the Loongson 3 family of CPUs in addition
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of the other MIPS CPUs. On the Loongson 3 family the MADD4 instructions
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are fused, while they are not fused on the other MIPS CPUs. In order to
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support both, we have to disabled those instructions.
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For that, the patch below basically corresponds to the --with-madd4=no
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used on the GCC side.
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Index: llvm-toolchain-10-10.0.1~+rc4/clang/lib/Basic/Targets/Mips.h
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===================================================================
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--- llvm-toolchain-10-10.0.1~+rc4.orig/clang/lib/Basic/Targets/Mips.h
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+++ llvm-toolchain-10-10.0.1~+rc4/clang/lib/Basic/Targets/Mips.h
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@@ -332,6 +332,8 @@
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HasMSA = true;
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else if (Feature == "+nomadd4")
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DisableMadd4 = true;
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+ else if (Feature == "-nomadd4")
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+ DisableMadd4 = false;
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else if (Feature == "+fp64")
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FPMode = FP64;
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else if (Feature == "-fp64")
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Index: llvm-toolchain-10-10.0.1~+rc4/llvm/lib/Target/Mips/MipsSubtarget.cpp
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===================================================================
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--- llvm-toolchain-10-10.0.1~+rc4.orig/llvm/lib/Target/Mips/MipsSubtarget.cpp
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+++ llvm-toolchain-10-10.0.1~+rc4/llvm/lib/Target/Mips/MipsSubtarget.cpp
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@@ -79,7 +79,7 @@
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InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
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InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), HasDSPR3(false),
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AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
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- UseTCCInDIV(false), HasSym32(false), HasEVA(false), DisableMadd4(false),
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+ UseTCCInDIV(false), HasSym32(false), HasEVA(false), DisableMadd4(true),
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HasMT(false), HasCRC(false), HasVirt(false), HasGINV(false),
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UseIndirectJumpsHazard(false), StackAlignOverride(StackAlignOverride),
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TM(TM), TargetTriple(TT), TSInfo(),
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@@ -91,6 +91,9 @@
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if (MipsArchVersion == MipsDefault)
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MipsArchVersion = Mips32;
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+ if (hasMips32r6() || hasMips64r6())
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+ DisableMadd4 = false;
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+
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// Don't even attempt to generate code for MIPS-I and MIPS-V. They have not
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// been tested and currently exist for the integrated assembler only.
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if (MipsArchVersion == Mips1)
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@@ -238,6 +241,7 @@
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MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
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const TargetMachine &TM) {
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std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
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+ SubtargetFeatures Features(FS);
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// Parse features string.
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ParseSubtargetFeatures(CPUName, FS);
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@@ -260,6 +264,13 @@
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report_fatal_error("64-bit code requested on a subtarget that doesn't "
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"support it!");
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+ for (const std::string &Feature : Features.getFeatures()) {
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+ if (Feature == "+nomadd4")
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+ DisableMadd4 = true;
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+ else if (Feature == "-nomadd4")
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+ DisableMadd4 = false;
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+ }
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+
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return *this;
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}
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Index: llvm-toolchain-10-10.0.1~+rc4/llvm/lib/Target/Mips/Mips.td
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===================================================================
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--- llvm-toolchain-10-10.0.1~+rc4.orig/llvm/lib/Target/Mips/Mips.td
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+++ llvm-toolchain-10-10.0.1~+rc4/llvm/lib/Target/Mips/Mips.td
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@@ -205,7 +205,7 @@
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"UseTCCInDIV", "false",
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"Force the assembler to use trapping">;
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-def FeatureMadd4
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+def FeatureNoMadd4
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: SubtargetFeature<"nomadd4", "DisableMadd4", "true",
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"Disable 4-operand madd.fmt and related instructions">;
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Index: llvm-toolchain-10-10.0.1~+rc4/llvm/lib/Target/Mips/MipsInstrInfo.td
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===================================================================
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--- llvm-toolchain-10-10.0.1~+rc4.orig/llvm/lib/Target/Mips/MipsInstrInfo.td
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+++ llvm-toolchain-10-10.0.1~+rc4/llvm/lib/Target/Mips/MipsInstrInfo.td
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@@ -242,7 +242,7 @@
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def HasMSA : Predicate<"Subtarget->hasMSA()">,
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AssemblerPredicate<"FeatureMSA">;
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def HasMadd4 : Predicate<"!Subtarget->disableMadd4()">,
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- AssemblerPredicate<"!FeatureMadd4">;
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+ AssemblerPredicate<"!FeatureNoMadd4">;
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def HasMT : Predicate<"Subtarget->hasMT()">,
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AssemblerPredicate<"FeatureMT">;
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def UseIndirectJumpsHazard : Predicate<"Subtarget->useIndirectJumpsHazard()">,
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