diff --git a/debian/patches/D74453-riscv-atomic_cmp_xchg.diff b/debian/patches/D74453-riscv-atomic_cmp_xchg.diff
index 32cc54c6..6fc71c0f 100644
--- a/debian/patches/D74453-riscv-atomic_cmp_xchg.diff
+++ b/debian/patches/D74453-riscv-atomic_cmp_xchg.diff
@@ -35,11 +35,11 @@ Differential Revision: https://reviews.llvm.org/D74453
  llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll      | 10 ++++++++++
  4 files changed, 43 insertions(+), 1 deletion(-)
 
-diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
-index fefa8daa60a1..99601c436651 100644
---- a/llvm/include/llvm/CodeGen/TargetLowering.h
-+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
-@@ -1962,6 +1962,18 @@ class TargetLoweringBase {
+Index: llvm-toolchain-10-10.0.0/llvm/include/llvm/CodeGen/TargetLowering.h
+===================================================================
+--- llvm-toolchain-10-10.0.0.orig/llvm/include/llvm/CodeGen/TargetLowering.h
++++ llvm-toolchain-10-10.0.0/llvm/include/llvm/CodeGen/TargetLowering.h
+@@ -1861,6 +1861,18 @@ public:
      return ISD::ZERO_EXTEND;
    }
  
@@ -58,11 +58,11 @@ index fefa8daa60a1..99601c436651 100644
    /// @}
  
    /// Returns true if we should normalize
-diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
-index 0248b5121e3f..ed67f7dc8ea3 100644
---- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
-+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
-@@ -278,8 +278,24 @@ SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
+Index: llvm-toolchain-10-10.0.0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+===================================================================
+--- llvm-toolchain-10-10.0.0.orig/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
++++ llvm-toolchain-10-10.0.0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+@@ -271,8 +271,24 @@ SDValue DAGTypeLegalizer::PromoteIntRes_
      return Res.getValue(1);
    }
  
@@ -88,11 +88,11 @@ index 0248b5121e3f..ed67f7dc8ea3 100644
    SDVTList VTs =
        DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
    SDValue Res = DAG.getAtomicCmpSwap(
-diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
-index 929169dd62d9..f76abf22e4db 100644
---- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
-+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
-@@ -129,6 +129,10 @@ class RISCVTargetLowering : public TargetLowering {
+Index: llvm-toolchain-10-10.0.0/llvm/lib/Target/RISCV/RISCVISelLowering.h
+===================================================================
+--- llvm-toolchain-10-10.0.0.orig/llvm/lib/Target/RISCV/RISCVISelLowering.h
++++ llvm-toolchain-10-10.0.0/llvm/lib/Target/RISCV/RISCVISelLowering.h
+@@ -127,6 +127,10 @@ public:
      return ISD::SIGN_EXTEND;
    }
  
@@ -103,11 +103,11 @@ index 929169dd62d9..f76abf22e4db 100644
    bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override {
      if (DAG.getMachineFunction().getFunction().hasMinSize())
        return false;
-diff --git a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
-index 43da05ebe7c7..f2691ba1a771 100644
---- a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
-+++ b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
-@@ -1628,6 +1628,7 @@ define void @cmpxchg_i32_monotonic_monotonic(i32* %ptr, i32 %cmp, i32 %val) noun
+Index: llvm-toolchain-10-10.0.0/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
+===================================================================
+--- llvm-toolchain-10-10.0.0.orig/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
++++ llvm-toolchain-10-10.0.0/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
+@@ -1628,6 +1628,7 @@ define void @cmpxchg_i32_monotonic_monot
  ;
  ; RV64IA-LABEL: cmpxchg_i32_monotonic_monotonic:
  ; RV64IA:       # %bb.0:
@@ -115,7 +115,7 @@ index 43da05ebe7c7..f2691ba1a771 100644
  ; RV64IA-NEXT:  .LBB20_1: # =>This Inner Loop Header: Depth=1
  ; RV64IA-NEXT:    lr.w a3, (a0)
  ; RV64IA-NEXT:    bne a3, a1, .LBB20_3
-@@ -1680,6 +1681,7 @@ define void @cmpxchg_i32_acquire_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwi
+@@ -1680,6 +1681,7 @@ define void @cmpxchg_i32_acquire_monoton
  ;
  ; RV64IA-LABEL: cmpxchg_i32_acquire_monotonic:
  ; RV64IA:       # %bb.0:
@@ -123,7 +123,7 @@ index 43da05ebe7c7..f2691ba1a771 100644
  ; RV64IA-NEXT:  .LBB21_1: # =>This Inner Loop Header: Depth=1
  ; RV64IA-NEXT:    lr.w.aq a3, (a0)
  ; RV64IA-NEXT:    bne a3, a1, .LBB21_3
-@@ -1732,6 +1734,7 @@ define void @cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind
+@@ -1732,6 +1734,7 @@ define void @cmpxchg_i32_acquire_acquire
  ;
  ; RV64IA-LABEL: cmpxchg_i32_acquire_acquire:
  ; RV64IA:       # %bb.0:
@@ -131,7 +131,7 @@ index 43da05ebe7c7..f2691ba1a771 100644
  ; RV64IA-NEXT:  .LBB22_1: # =>This Inner Loop Header: Depth=1
  ; RV64IA-NEXT:    lr.w.aq a3, (a0)
  ; RV64IA-NEXT:    bne a3, a1, .LBB22_3
-@@ -1784,6 +1787,7 @@ define void @cmpxchg_i32_release_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwi
+@@ -1784,6 +1787,7 @@ define void @cmpxchg_i32_release_monoton
  ;
  ; RV64IA-LABEL: cmpxchg_i32_release_monotonic:
  ; RV64IA:       # %bb.0:
@@ -139,7 +139,7 @@ index 43da05ebe7c7..f2691ba1a771 100644
  ; RV64IA-NEXT:  .LBB23_1: # =>This Inner Loop Header: Depth=1
  ; RV64IA-NEXT:    lr.w a3, (a0)
  ; RV64IA-NEXT:    bne a3, a1, .LBB23_3
-@@ -1836,6 +1840,7 @@ define void @cmpxchg_i32_release_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind
+@@ -1836,6 +1840,7 @@ define void @cmpxchg_i32_release_acquire
  ;
  ; RV64IA-LABEL: cmpxchg_i32_release_acquire:
  ; RV64IA:       # %bb.0:
@@ -147,7 +147,7 @@ index 43da05ebe7c7..f2691ba1a771 100644
  ; RV64IA-NEXT:  .LBB24_1: # =>This Inner Loop Header: Depth=1
  ; RV64IA-NEXT:    lr.w a3, (a0)
  ; RV64IA-NEXT:    bne a3, a1, .LBB24_3
-@@ -1888,6 +1893,7 @@ define void @cmpxchg_i32_acq_rel_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwi
+@@ -1888,6 +1893,7 @@ define void @cmpxchg_i32_acq_rel_monoton
  ;
  ; RV64IA-LABEL: cmpxchg_i32_acq_rel_monotonic:
  ; RV64IA:       # %bb.0:
@@ -155,7 +155,7 @@ index 43da05ebe7c7..f2691ba1a771 100644
  ; RV64IA-NEXT:  .LBB25_1: # =>This Inner Loop Header: Depth=1
  ; RV64IA-NEXT:    lr.w.aq a3, (a0)
  ; RV64IA-NEXT:    bne a3, a1, .LBB25_3
-@@ -1940,6 +1946,7 @@ define void @cmpxchg_i32_acq_rel_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind
+@@ -1940,6 +1946,7 @@ define void @cmpxchg_i32_acq_rel_acquire
  ;
  ; RV64IA-LABEL: cmpxchg_i32_acq_rel_acquire:
  ; RV64IA:       # %bb.0:
@@ -163,7 +163,7 @@ index 43da05ebe7c7..f2691ba1a771 100644
  ; RV64IA-NEXT:  .LBB26_1: # =>This Inner Loop Header: Depth=1
  ; RV64IA-NEXT:    lr.w.aq a3, (a0)
  ; RV64IA-NEXT:    bne a3, a1, .LBB26_3
-@@ -1992,6 +1999,7 @@ define void @cmpxchg_i32_seq_cst_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwi
+@@ -1992,6 +1999,7 @@ define void @cmpxchg_i32_seq_cst_monoton
  ;
  ; RV64IA-LABEL: cmpxchg_i32_seq_cst_monotonic:
  ; RV64IA:       # %bb.0:
@@ -171,7 +171,7 @@ index 43da05ebe7c7..f2691ba1a771 100644
  ; RV64IA-NEXT:  .LBB27_1: # =>This Inner Loop Header: Depth=1
  ; RV64IA-NEXT:    lr.w.aqrl a3, (a0)
  ; RV64IA-NEXT:    bne a3, a1, .LBB27_3
-@@ -2044,6 +2052,7 @@ define void @cmpxchg_i32_seq_cst_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind
+@@ -2044,6 +2052,7 @@ define void @cmpxchg_i32_seq_cst_acquire
  ;
  ; RV64IA-LABEL: cmpxchg_i32_seq_cst_acquire:
  ; RV64IA:       # %bb.0:
@@ -179,7 +179,7 @@ index 43da05ebe7c7..f2691ba1a771 100644
  ; RV64IA-NEXT:  .LBB28_1: # =>This Inner Loop Header: Depth=1
  ; RV64IA-NEXT:    lr.w.aqrl a3, (a0)
  ; RV64IA-NEXT:    bne a3, a1, .LBB28_3
-@@ -2096,6 +2105,7 @@ define void @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 %cmp, i32 %val) nounwind
+@@ -2096,6 +2105,7 @@ define void @cmpxchg_i32_seq_cst_seq_cst
  ;
  ; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
  ; RV64IA:       # %bb.0: