Merge branch 'fix-riscv64' into '9'

llvm-riscv64-fix-cffi.diff: backport patch to fix CFI directives on riscv64 from master.

See merge request pkg-llvm-team/llvm-toolchain!45

debian/changelog

@@ -1,5 +1,6 @@
 llvm-toolchain-9 (1:9.0.1~+rc2-1~exp2) UNRELEASED; urgency=medium
 
+  [ Sylvestre Ledru ]
   * Use secure URI in debian/watch.
   * Move source package lintian overrides to debian/source.
   * Remove patches force-gcc-header-obj.diff, hurd-pathmax.diff, impl-
@@ -10,6 +11,10 @@ llvm-toolchain-9 (1:9.0.1~+rc2-1~exp2) UNRELEASED; urgency=medium
   * Move transitional package libclang-cpp1-9 to oldlibs/optional per
     policy 4.0.1.
 
+  [ Aurelien Jarno ]
+  * llvm-riscv64-fix-cffi.diff: backport patch to fix CFI directives on
+    riscv64 from master.
+
  -- Sylvestre Ledru <sylvestre@debian.org>  Sun, 08 Dec 2019 21:02:49 +0100
 
 llvm-toolchain-9 (1:9.0.1~+rc2-1~exp1) experimental; urgency=medium

debian/patches/llvm-riscv64-fix-cffi.diff

@@ -0,0 +1,76 @@
+commit c6b09bff5671600f8e764d3847023d0996f328d9
+Author: Luís Marques <luismarques@lowrisc.org>
+Date:   Thu Nov 14 18:27:42 2019 +0000
+
+    [RISCV] Fix wrong CFI directives
+
+    Summary: Removes CFI CFA directives that could incorrectly propagate
+    beyond the basic block they were inteded for. Specifically it removes
+    the epilogue CFI directives. See the branch_and_tail_call test for an
+    example of the issue. Should fix the stack unwinding issues caused by
+    the incorrect directives.
+
+    Reviewers: asb, lenary, shiva0217
+    Reviewed By: lenary
+    Tags: #llvm
+    Differential Revision: https://reviews.llvm.org/D69723
+
+--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
++++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+@@ -205,7 +205,6 @@
+   MachineFrameInfo &MFI = MF.getFrameInfo();
+   auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
+   DebugLoc DL = MBBI->getDebugLoc();
+-  const RISCVInstrInfo *TII = STI.getInstrInfo();
+   unsigned FPReg = getFPReg(STI);
+   unsigned SPReg = getSPReg(STI);
+ 
+@@ -225,48 +224,9 @@
+     adjustReg(MBB, LastFrameDestroy, DL, SPReg, FPReg, -FPOffset,
+               MachineInstr::FrameDestroy);
+   }
+-
+-  if (hasFP(MF)) {
+-    // To find the instruction restoring FP from stack.
+-    for (auto &I = LastFrameDestroy; I != MBBI; ++I) {
+-      if (I->mayLoad() && I->getOperand(0).isReg()) {
+-        unsigned DestReg = I->getOperand(0).getReg();
+-        if (DestReg == FPReg) {
+-          // If there is frame pointer, after restoring $fp registers, we
+-          // need adjust CFA to ($sp - FPOffset).
+-          // Emit ".cfi_def_cfa $sp, -FPOffset"
+-          unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
+-              nullptr, RI->getDwarfRegNum(SPReg, true), -FPOffset));
+-          BuildMI(MBB, std::next(I), DL,
+-                  TII->get(TargetOpcode::CFI_INSTRUCTION))
+-              .addCFIIndex(CFIIndex);
+-          break;
+-        }
+-      }
+-    }
+-  }
+-
+-  // Add CFI directives for callee-saved registers.
+-  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
+-  // Iterate over list of callee-saved registers and emit .cfi_restore
+-  // directives.
+-  for (const auto &Entry : CSI) {
+-    unsigned Reg = Entry.getReg();
+-    unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
+-        nullptr, RI->getDwarfRegNum(Reg, true)));
+-    BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
+-        .addCFIIndex(CFIIndex);
+-  }
+ 
+   // Deallocate stack
+   adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy);
+-
+-  // After restoring $sp, we need to adjust CFA to $(sp + 0)
+-  // Emit ".cfi_def_cfa_offset 0"
+-  unsigned CFIIndex =
+-      MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
+-  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
+-      .addCFIIndex(CFIIndex);
+ }
+ 
+ int RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF,

debian/patches/series

@@ -128,6 +128,7 @@ bootstrap-fix-include-next.diff
 # riscv64
 clang-riscv64-multiarch.diff
 clang-riscv64-rv64gc.diff
+llvm-riscv64-fix-cffi.diff
 
 #try-to-unbreak-thinlto.diff
 D67877.patch