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Drop powerpcspe patches merged upstream
- debian/patches/powerpcspe/D49754-powerpcspe-clang.diff - debian/patches/powerpcspe/D54583-powerpcspe-double-parameter.diff - debian/patches/powerpcspe/D56703-powerpcspe-register-spilling.diff
This commit is contained in:
John Paul Adrian Glaubitz
parent
3940bfdc70
commit
c8c26a6374
4
debian/changelog
vendored
4
debian/changelog
vendored
@ -21,6 +21,10 @@ llvm-toolchain-snapshot (1:12~++20200804122259+4be13b15d69-1~exp1) UNRELEASED; u
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* Link against libatomic on powerpc to fix FTBFS in stage2
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* Use dh-exec to exclude lib/libPolly*.a on powerpc and
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powerpcspe from libclang-common-X.Y-dev.install.in
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* Drop powerpcspe patches merged upstream:
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- debian/patches/powerpcspe/D49754-powerpcspe-clang.diff
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- debian/patches/powerpcspe/D54583-powerpcspe-double-parameter.diff
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- debian/patches/powerpcspe/D56703-powerpcspe-register-spilling.diff
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-- Sylvestre Ledru <sylvestre@debian.org> Tue, 04 Aug 2020 12:26:34 +0200
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@ -1,164 +0,0 @@
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Description: Add -m(no-)spe, and e500 CPU definitions and support to clang
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Author: Justin Hibbits <jrh29@alumni.cwru.edu>
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Origin: https://reviews.llvm.org/D49754
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Last-Update: 2019-02-14
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--- llvm-toolchain-snapshot-9~svn351420.orig/clang/include/clang/Driver/Options.td
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+++ llvm-toolchain-snapshot-9~svn351420/clang/include/clang/Driver/Options.td
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@@ -2180,6 +2180,8 @@ def faltivec : Flag<["-"], "faltivec">,
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def fno_altivec : Flag<["-"], "fno-altivec">, Group<f_Group>, Flags<[DriverOption]>;
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def maltivec : Flag<["-"], "maltivec">, Group<m_ppc_Features_Group>;
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def mno_altivec : Flag<["-"], "mno-altivec">, Group<m_ppc_Features_Group>;
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+def mspe : Flag<["-"], "mspe">, Group<m_ppc_Features_Group>;
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+def mno_spe : Flag<["-"], "mno-spe">, Group<m_ppc_Features_Group>;
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def mvsx : Flag<["-"], "mvsx">, Group<m_ppc_Features_Group>;
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def mno_vsx : Flag<["-"], "mno-vsx">, Group<m_ppc_Features_Group>;
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def msecure_plt : Flag<["-"], "msecure-plt">, Group<m_ppc_Features_Group>;
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--- llvm-toolchain-snapshot-9~svn351420.orig/clang/lib/Basic/Targets/PPC.cpp
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+++ llvm-toolchain-snapshot-9~svn351420/clang/lib/Basic/Targets/PPC.cpp
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@@ -54,6 +54,10 @@ bool PPCTargetInfo::handleTargetFeatures
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HasFloat128 = true;
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} else if (Feature == "+power9-vector") {
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HasP9Vector = true;
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+ } else if (Feature == "+spe") {
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+ HasSPE = true;
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+ LongDoubleWidth = LongDoubleAlign = 64;
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+ LongDoubleFormat = &llvm::APFloat::IEEEdouble();
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}
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// TODO: Finish this list and add an assert that we've handled them
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// all.
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@@ -161,6 +165,10 @@ void PPCTargetInfo::getTargetDefines(con
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Builder.defineMacro("__VEC__", "10206");
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Builder.defineMacro("__ALTIVEC__");
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}
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+ if (HasSPE) {
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+ Builder.defineMacro("__SPE__");
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+ Builder.defineMacro("__NO_FPRS__");
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+ }
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if (HasVSX)
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Builder.defineMacro("__VSX__");
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if (HasP8Vector)
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@@ -306,6 +314,11 @@ bool PPCTargetInfo::initFeatureMap(
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.Case("pwr8", true)
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.Default(false);
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+ Features["spe"] = llvm::StringSwitch<bool>(CPU)
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+ .Case("e500", true)
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+ .Case("8548", true)
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+ .Default(false);
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+
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if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
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return false;
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@@ -334,6 +347,7 @@ bool PPCTargetInfo::hasFeature(StringRef
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.Case("extdiv", HasExtDiv)
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.Case("float128", HasFloat128)
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.Case("power9-vector", HasP9Vector)
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+ .Case("spe", HasSPE)
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.Default(false);
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}
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@@ -443,16 +457,16 @@ ArrayRef<TargetInfo::AddlRegName> PPCTar
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}
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static constexpr llvm::StringLiteral ValidCPUNames[] = {
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- {"generic"}, {"440"}, {"450"}, {"601"}, {"602"},
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- {"603"}, {"603e"}, {"603ev"}, {"604"}, {"604e"},
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- {"620"}, {"630"}, {"g3"}, {"7400"}, {"g4"},
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- {"7450"}, {"g4+"}, {"750"}, {"970"}, {"g5"},
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- {"a2"}, {"a2q"}, {"e500mc"}, {"e5500"}, {"power3"},
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- {"pwr3"}, {"power4"}, {"pwr4"}, {"power5"}, {"pwr5"},
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- {"power5x"}, {"pwr5x"}, {"power6"}, {"pwr6"}, {"power6x"},
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- {"pwr6x"}, {"power7"}, {"pwr7"}, {"power8"}, {"pwr8"},
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- {"power9"}, {"pwr9"}, {"powerpc"}, {"ppc"}, {"powerpc64"},
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- {"ppc64"}, {"powerpc64le"}, {"ppc64le"},
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+ {"generic"}, {"440"}, {"450"}, {"601"}, {"602"},
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+ {"603"}, {"603e"}, {"603ev"}, {"604"}, {"604e"},
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+ {"620"}, {"630"}, {"g3"}, {"7400"}, {"g4"},
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+ {"7450"}, {"g4+"}, {"750"}, {"8548"}, {"970"},
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+ {"g5"}, {"a2"}, {"a2q"}, {"e500"}, {"e500mc"},
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+ {"e5500"}, {"power3"}, {"pwr3"}, {"power4"}, {"pwr4"},
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+ {"power5"}, {"pwr5"}, {"power5x"}, {"pwr5x"}, {"power6"},
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+ {"pwr6"}, {"power6x"}, {"pwr6x"}, {"power7"}, {"pwr7"},
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+ {"power8"}, {"pwr8"}, {"power9"}, {"pwr9"}, {"powerpc"},
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+ {"ppc"}, {"powerpc64"}, {"ppc64"}, {"powerpc64le"}, {"ppc64le"},
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};
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bool PPCTargetInfo::isValidCPUName(StringRef Name) const {
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--- llvm-toolchain-snapshot-9~svn351420.orig/clang/lib/Basic/Targets/PPC.h
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+++ llvm-toolchain-snapshot-9~svn351420/clang/lib/Basic/Targets/PPC.h
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@@ -45,7 +45,8 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetI
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ArchDefinePwr8 = 1 << 12,
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ArchDefinePwr9 = 1 << 13,
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ArchDefineA2 = 1 << 14,
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- ArchDefineA2q = 1 << 15
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+ ArchDefineA2q = 1 << 15,
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+ ArchDefine500v2 = 1 << 16
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} ArchDefineTypes;
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@@ -66,6 +67,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetI
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bool HasBPERMD = false;
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bool HasExtDiv = false;
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bool HasP9Vector = false;
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+ bool HasSPE = false;
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protected:
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std::string ABI;
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@@ -145,6 +147,8 @@ public:
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ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
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ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
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ArchDefinePpcsq)
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+ .Cases("e500", "e500v2",
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+ ArchDefineName | ArchDefine500v2)
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.Default(ArchDefineNone);
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}
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return CPUKnown;
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--- llvm-toolchain-snapshot-9~svn351420.orig/clang/lib/CodeGen/TargetInfo.cpp
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+++ llvm-toolchain-snapshot-9~svn351420/clang/lib/CodeGen/TargetInfo.cpp
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@@ -9316,7 +9316,8 @@ const TargetCodeGenInfo &CodeGenModule::
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case llvm::Triple::ppc:
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return SetCGInfo(
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- new PPC32TargetCodeGenInfo(Types, CodeGenOpts.FloatABI == "soft"));
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+ new PPC32TargetCodeGenInfo(Types, CodeGenOpts.FloatABI == "soft" ||
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+ getTarget().hasFeature("spe")));
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case llvm::Triple::ppc64:
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if (Triple.isOSBinFormatELF()) {
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PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv1;
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--- llvm-toolchain-snapshot-9~svn351420.orig/clang/test/Driver/ppc-features.cpp
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+++ llvm-toolchain-snapshot-9~svn351420/clang/test/Driver/ppc-features.cpp
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@@ -168,6 +168,9 @@
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// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-invariant-function-descriptors -minvariant-function-descriptors -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-INVFUNCDESC %s
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// CHECK-INVFUNCDESC: "-target-feature" "+invariant-function-descriptors"
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+// RUN: %clang -target powerpc-unknown-linux-gnu %s -mno-spe -mspe -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-SPE %s
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+// CHECK-SPE: "-target-feature" "+spe"
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+
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// Assembler features
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// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -o %t.o -no-integrated-as 2>&1 | FileCheck -check-prefix=CHECK_BE_AS_ARGS %s
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// CHECK_BE_AS_ARGS: "-mppc64"
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--- llvm-toolchain-snapshot-9~svn351420.orig/clang/test/Misc/target-invalid-cpu-note.c
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+++ llvm-toolchain-snapshot-9~svn351420/clang/test/Misc/target-invalid-cpu-note.c
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@@ -79,7 +79,7 @@
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// PPC: error: unknown target CPU 'not-a-cpu'
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// PPC: note: valid target CPU values are: generic, 440, 450, 601, 602, 603,
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// PPC-SAME: 603e, 603ev, 604, 604e, 620, 630, g3, 7400, g4, 7450, g4+, 750,
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-// PPC-SAME: 970, g5, a2, a2q, e500mc, e5500, power3, pwr3, power4, pwr4,
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+// PPC-SAME: 970, g5, a2, a2q, e500, e500mc, e5500, power3, pwr3, power4, pwr4,
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// PPC-SAME: power5, pwr5, power5x, pwr5x, power6, pwr6, power6x, pwr6x, power7,
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// PPC-SAME: pwr7, power8, pwr8, power9, pwr9, powerpc, ppc, powerpc64, ppc64,
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// PPC-SAME: powerpc64le, ppc64le
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--- llvm-toolchain-snapshot-9~svn351420.orig/clang/test/Preprocessor/init.c
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+++ llvm-toolchain-snapshot-9~svn351420/clang/test/Preprocessor/init.c
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@@ -7016,6 +7016,10 @@
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//
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// PPC32-LINUX-NOT: _CALL_LINUX
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//
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+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc-unknown-linux-gnu -target-feature +spe < /dev/null | FileCheck -match-full-lines -check-prefix PPC32-SPE %s
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+//
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+// PPC32-SPE:#define __SPE__ 1
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+//
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// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc-apple-darwin8 < /dev/null | FileCheck -match-full-lines -check-prefix PPC-DARWIN %s
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//
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// PPC-DARWIN:#define _ARCH_PPC 1
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@ -1,420 +0,0 @@
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Description: PowerPC: Optimize SPE double parameter calling setup
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Author: Justin Hibbits <jrh29@alumni.cwru.edu>
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Origin: https://reviews.llvm.org/D54583
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Last-Update: 2019-02-14
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--- llvm-toolchain-snapshot-9~svn351420.orig/lib/Target/PowerPC/PPCCallingConv.td
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+++ llvm-toolchain-snapshot-9~svn351420/lib/Target/PowerPC/PPCCallingConv.td
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@@ -90,7 +90,7 @@ def RetCC_PPC : CallingConv<[
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CCIfSubtarget<"hasSPE()",
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CCIfType<[f32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
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CCIfSubtarget<"hasSPE()",
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- CCIfType<[f64], CCAssignToReg<[S3, S4, S5, S6, S7, S8, S9, S10]>>>,
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+ CCIfType<[f64], CCCustom<"CC_PPC32_SPE_RetF64">>>,
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// For P9, f128 are passed in vector registers.
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CCIfType<[f128],
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@@ -179,6 +179,9 @@ def CC_PPC32_SVR4_Common : CallingConv<[
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CCIfType<[i32],
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CCIfSplit<CCIfNotSubtarget<"useSoftFloat()",
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CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>>,
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+ CCIfType<[f64],
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+ CCIfSubtarget<"hasSPE()",
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+ CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>,
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CCIfSplit<CCIfSubtarget<"useSoftFloat()",
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CCIfOrigArgWasPPCF128<CCCustom<
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"CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128">>>>,
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@@ -199,7 +202,7 @@ def CC_PPC32_SVR4_Common : CallingConv<[
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CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>>,
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CCIfType<[f64],
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CCIfSubtarget<"hasSPE()",
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- CCAssignToReg<[S3, S4, S5, S6, S7, S8, S9, S10]>>>,
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+ CCCustom<"CC_PPC32_SPE_CustomSplitFP64">>>,
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CCIfType<[f32],
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CCIfSubtarget<"hasSPE()",
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CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
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--- llvm-toolchain-snapshot-9~svn351420.orig/lib/Target/PowerPC/PPCISelLowering.cpp
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+++ llvm-toolchain-snapshot-9~svn351420/lib/Target/PowerPC/PPCISelLowering.cpp
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@@ -1232,22 +1232,6 @@ unsigned PPCTargetLowering::getByValType
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return Align;
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}
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-unsigned PPCTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
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- CallingConv:: ID CC,
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- EVT VT) const {
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- if (Subtarget.hasSPE() && VT == MVT::f64)
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- return 2;
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- return PPCTargetLowering::getNumRegisters(Context, VT);
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-}
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-
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-MVT PPCTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
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- CallingConv:: ID CC,
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- EVT VT) const {
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- if (Subtarget.hasSPE() && VT == MVT::f64)
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- return MVT::i32;
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- return PPCTargetLowering::getRegisterType(Context, VT);
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-}
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-
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bool PPCTargetLowering::useSoftFloat() const {
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return Subtarget.useSoftFloat();
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}
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@@ -1365,6 +1349,8 @@ const char *PPCTargetLowering::getTarget
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case PPCISD::QBFLT: return "PPCISD::QBFLT";
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case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
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case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128";
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+ case PPCISD::BUILD_SPE64: return "PPCISD::BUILD_SPE64";
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+ case PPCISD::EXTRACT_SPE: return "PPCISD::EXTRACT_SPE";
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case PPCISD::EXTSWSLI: return "PPCISD::EXTSWSLI";
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}
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return nullptr;
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@@ -3162,6 +3148,58 @@ bool llvm::CC_PPC32_SVR4_Custom_Dummy(un
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return true;
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}
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+bool llvm::CC_PPC32_SPE_CustomSplitFP64(unsigned &ValNo, MVT &ValVT,
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+ MVT &LocVT,
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+ CCValAssign::LocInfo &LocInfo,
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+ ISD::ArgFlagsTy &ArgFlags,
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+ CCState &State) {
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+ static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 };
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+ static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 };
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+
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+ // Try to get the first register.
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+ unsigned Reg = State.AllocateReg(HiRegList);
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+ if (!Reg)
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+ return false;
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+
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+ unsigned i;
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+ for (i = 0; i < sizeof(HiRegList) / sizeof(HiRegList[0]); ++i)
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+ if (HiRegList[i] == Reg)
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+ break;
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+
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+ unsigned T = State.AllocateReg(LoRegList[i]);
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+ (void)T;
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+ assert(T == LoRegList[i] && "Could not allocate register");
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+
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+ State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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+ State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
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+ LocVT, LocInfo));
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+ return true;
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+}
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+
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+bool llvm::CC_PPC32_SPE_RetF64(unsigned &ValNo, MVT &ValVT,
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+ MVT &LocVT,
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+ CCValAssign::LocInfo &LocInfo,
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+ ISD::ArgFlagsTy &ArgFlags,
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+ CCState &State) {
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+ static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 };
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+ static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 };
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+
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+ // Try to get the first register.
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+ unsigned Reg = State.AllocateReg(HiRegList);
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+ if (!Reg)
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+ return false;
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+
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+ unsigned i;
|
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+ for (i = 0; i < sizeof(HiRegList) / sizeof(HiRegList[0]); ++i)
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+ if (HiRegList[i] == Reg)
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+ break;
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+
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+ State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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+ State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
|
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+ LocVT, LocInfo));
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+ return true;
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+}
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+
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bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
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MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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@@ -3449,7 +3487,7 @@ SDValue PPCTargetLowering::LowerFormalAr
|
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// Reserve space for the linkage area on the stack.
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unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
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CCInfo.AllocateStack(LinkageSize, PtrByteSize);
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- if (useSoftFloat() || hasSPE())
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+ if (useSoftFloat())
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CCInfo.PreAnalyzeFormalArguments(Ins);
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|
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CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
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@@ -3482,7 +3520,8 @@ SDValue PPCTargetLowering::LowerFormalAr
|
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if (Subtarget.hasVSX())
|
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RC = &PPC::VSFRCRegClass;
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else if (Subtarget.hasSPE())
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- RC = &PPC::SPERCRegClass;
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+ // SPE passes doubles in GPR pairs.
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+ RC = &PPC::GPRCRegClass;
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else
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RC = &PPC::F8RCRegClass;
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break;
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@@ -3506,13 +3545,30 @@ SDValue PPCTargetLowering::LowerFormalAr
|
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break;
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}
|
||||
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- // Transform the arguments stored in physical registers into virtual ones.
|
||||
- unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
|
||||
- SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
|
||||
- ValVT == MVT::i1 ? MVT::i32 : ValVT);
|
||||
+ SDValue ArgValue;
|
||||
+ if (VA.getLocVT() == MVT::f64 && Subtarget.hasSPE()) {
|
||||
+ // Transform the arguments stored in physical registers into
|
||||
+ // virtual ones.
|
||||
+ unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
|
||||
+ ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
|
||||
+
|
||||
+ SDValue ArgValue2;
|
||||
+ Reg = MF.addLiveIn(ArgLocs[++i].getLocReg(), RC);
|
||||
+ ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
|
||||
+ if (!Subtarget.isLittleEndian())
|
||||
+ std::swap (ArgValue, ArgValue2);
|
||||
+ ArgValue = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, ArgValue,
|
||||
+ ArgValue2);
|
||||
+ } else {
|
||||
|
||||
- if (ValVT == MVT::i1)
|
||||
- ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
|
||||
+ // Transform the arguments stored in physical registers into
|
||||
+ // virtual ones.
|
||||
+ unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
|
||||
+ ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
|
||||
+ ValVT == MVT::i1 ? MVT::i32 : ValVT);
|
||||
+ if (ValVT == MVT::i1)
|
||||
+ ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
|
||||
+ }
|
||||
|
||||
InVals.push_back(ArgValue);
|
||||
} else {
|
||||
@@ -5129,10 +5185,27 @@ SDValue PPCTargetLowering::LowerCallResu
|
||||
CCValAssign &VA = RVLocs[i];
|
||||
assert(VA.isRegLoc() && "Can only return in registers!");
|
||||
|
||||
- SDValue Val = DAG.getCopyFromReg(Chain, dl,
|
||||
- VA.getLocReg(), VA.getLocVT(), InFlag);
|
||||
- Chain = Val.getValue(1);
|
||||
- InFlag = Val.getValue(2);
|
||||
+ SDValue Val;
|
||||
+
|
||||
+ if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) {
|
||||
+ SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
|
||||
+ InFlag);
|
||||
+ Chain = Lo.getValue(1);
|
||||
+ InFlag = Lo.getValue(2);
|
||||
+ VA = RVLocs[++i]; // skip ahead to next loc
|
||||
+ SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
|
||||
+ InFlag);
|
||||
+ Chain = Hi.getValue(1);
|
||||
+ InFlag = Hi.getValue(2);
|
||||
+ if (!Subtarget.isLittleEndian())
|
||||
+ std::swap (Lo, Hi);
|
||||
+ Val = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, Lo, Hi);
|
||||
+ } else {
|
||||
+ Val = DAG.getCopyFromReg(Chain, dl,
|
||||
+ VA.getLocReg(), VA.getLocVT(), InFlag);
|
||||
+ Chain = Val.getValue(1);
|
||||
+ InFlag = Val.getValue(2);
|
||||
+ }
|
||||
|
||||
switch (VA.getLocInfo()) {
|
||||
default: llvm_unreachable("Unknown loc info!");
|
||||
@@ -5444,12 +5517,12 @@ SDValue PPCTargetLowering::LowerCall_32S
|
||||
|
||||
bool seenFloatArg = false;
|
||||
// Walk the register/memloc assignments, inserting copies/loads.
|
||||
- for (unsigned i = 0, j = 0, e = ArgLocs.size();
|
||||
+ for (unsigned i = 0, realI = 0, j = 0, e = ArgLocs.size();
|
||||
i != e;
|
||||
- ++i) {
|
||||
+ ++i, ++realI) {
|
||||
CCValAssign &VA = ArgLocs[i];
|
||||
- SDValue Arg = OutVals[i];
|
||||
- ISD::ArgFlagsTy Flags = Outs[i].Flags;
|
||||
+ SDValue Arg = OutVals[realI];
|
||||
+ ISD::ArgFlagsTy Flags = Outs[realI].Flags;
|
||||
|
||||
if (Flags.isByVal()) {
|
||||
// Argument is an aggregate which is passed by value, thus we need to
|
||||
@@ -5498,7 +5571,18 @@ SDValue PPCTargetLowering::LowerCall_32S
|
||||
if (VA.isRegLoc()) {
|
||||
seenFloatArg |= VA.getLocVT().isFloatingPoint();
|
||||
// Put argument in a physical register.
|
||||
- RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
|
||||
+ if (Subtarget.hasSPE() && Arg.getValueType() == MVT::f64) {
|
||||
+ unsigned id = Subtarget.isLittleEndian() ? 0 : 1;
|
||||
+ SDValue SVal = DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg,
|
||||
+ DAG.getIntPtrConstant(id, dl));
|
||||
+ RegsToPass.push_back(std::make_pair(VA.getLocReg(), SVal.getValue(0)));
|
||||
+ SVal = DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg,
|
||||
+ DAG.getIntPtrConstant(1 - id, dl));
|
||||
+
|
||||
+ RegsToPass.push_back(std::make_pair(ArgLocs[++i].getLocReg(),
|
||||
+ SVal.getValue(0)));
|
||||
+ } else
|
||||
+ RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
|
||||
} else {
|
||||
// Put argument in the parameter list area of the current stack frame.
|
||||
assert(VA.isMemLoc());
|
||||
@@ -6644,11 +6728,11 @@ PPCTargetLowering::LowerReturn(SDValue C
|
||||
SmallVector<SDValue, 4> RetOps(1, Chain);
|
||||
|
||||
// Copy the result values into the output registers.
|
||||
- for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
||||
+ for (unsigned i = 0, realI = 0; i != RVLocs.size(); ++i, ++realI) {
|
||||
CCValAssign &VA = RVLocs[i];
|
||||
assert(VA.isRegLoc() && "Can only return in registers!");
|
||||
|
||||
- SDValue Arg = OutVals[i];
|
||||
+ SDValue Arg = OutVals[realI];
|
||||
|
||||
switch (VA.getLocInfo()) {
|
||||
default: llvm_unreachable("Unknown loc info!");
|
||||
@@ -6663,8 +6747,21 @@ PPCTargetLowering::LowerReturn(SDValue C
|
||||
Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
|
||||
break;
|
||||
}
|
||||
-
|
||||
- Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
|
||||
+ if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) {
|
||||
+ bool isLittleEndian = Subtarget.isLittleEndian();
|
||||
+ // Legalize ret f64 -> ret 2 x i32.
|
||||
+ SDValue SVal =
|
||||
+ DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg,
|
||||
+ DAG.getIntPtrConstant(isLittleEndian ? 0 : 1, dl));
|
||||
+ Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), SVal, Flag);
|
||||
+ RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
|
||||
+ SVal = DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg,
|
||||
+ DAG.getIntPtrConstant(isLittleEndian ? 1 : 0, dl));
|
||||
+ Flag = Chain.getValue(1);
|
||||
+ VA = RVLocs[++i]; // skip ahead to next loc
|
||||
+ Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), SVal, Flag);
|
||||
+ } else
|
||||
+ Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
|
||||
Flag = Chain.getValue(1);
|
||||
RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
|
||||
}
|
||||
--- llvm-toolchain-snapshot-9~svn351420.orig/lib/Target/PowerPC/PPCISelLowering.h
|
||||
+++ llvm-toolchain-snapshot-9~svn351420/lib/Target/PowerPC/PPCISelLowering.h
|
||||
@@ -196,6 +196,15 @@ namespace llvm {
|
||||
/// Direct move of 2 consective GPR to a VSX register.
|
||||
BUILD_FP128,
|
||||
|
||||
+ /// BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and
|
||||
+ /// EXTRACT_ELEMENT but take f64 arguments instead of i64, as i64 is
|
||||
+ /// unsupported for this target.
|
||||
+ /// Merge 2 GPRs to a single SPE register.
|
||||
+ BUILD_SPE64,
|
||||
+
|
||||
+ /// Extract SPE register component, second argument is high or low.
|
||||
+ EXTRACT_SPE,
|
||||
+
|
||||
/// Extract a subvector from signed integer vector and convert to FP.
|
||||
/// It is primarily used to convert a (widened) illegal integer vector
|
||||
/// type to a legal floating point vector type.
|
||||
@@ -898,14 +907,6 @@ namespace llvm {
|
||||
unsigned JTI,
|
||||
MCContext &Ctx) const override;
|
||||
|
||||
- unsigned getNumRegistersForCallingConv(LLVMContext &Context,
|
||||
- CallingConv:: ID CC,
|
||||
- EVT VT) const override;
|
||||
-
|
||||
- MVT getRegisterTypeForCallingConv(LLVMContext &Context,
|
||||
- CallingConv:: ID CC,
|
||||
- EVT VT) const override;
|
||||
-
|
||||
private:
|
||||
struct ReuseLoadInfo {
|
||||
SDValue Ptr;
|
||||
@@ -1110,6 +1111,7 @@ namespace llvm {
|
||||
SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
|
||||
+ SDValue LowerEXTRACT_ELEMENT(SDValue Op, SelectionDAG &DAG) const;
|
||||
|
||||
SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
|
||||
SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const;
|
||||
@@ -1187,6 +1189,17 @@ namespace llvm {
|
||||
ISD::ArgFlagsTy &ArgFlags,
|
||||
CCState &State);
|
||||
|
||||
+ bool CC_PPC32_SPE_CustomSplitFP64(unsigned &ValNo, MVT &ValVT,
|
||||
+ MVT &LocVT,
|
||||
+ CCValAssign::LocInfo &LocInfo,
|
||||
+ ISD::ArgFlagsTy &ArgFlags,
|
||||
+ CCState &State);
|
||||
+ bool CC_PPC32_SPE_RetF64(unsigned &ValNo, MVT &ValVT,
|
||||
+ MVT &LocVT,
|
||||
+ CCValAssign::LocInfo &LocInfo,
|
||||
+ ISD::ArgFlagsTy &ArgFlags,
|
||||
+ CCState &State);
|
||||
+
|
||||
bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
|
||||
MVT &LocVT,
|
||||
CCValAssign::LocInfo &LocInfo,
|
||||
--- llvm-toolchain-snapshot-9~svn351420.orig/lib/Target/PowerPC/PPCInstrInfo.td
|
||||
+++ llvm-toolchain-snapshot-9~svn351420/lib/Target/PowerPC/PPCInstrInfo.td
|
||||
@@ -231,6 +231,17 @@ def PPCbuild_fp128: SDNode<"PPCISD::BUIL
|
||||
SDTCisSameAs<1,2>]>,
|
||||
[]>;
|
||||
|
||||
+def PPCbuild_spe64: SDNode<"PPCISD::BUILD_SPE64",
|
||||
+ SDTypeProfile<1, 2,
|
||||
+ [SDTCisFP<0>, SDTCisSameSizeAs<1,2>,
|
||||
+ SDTCisSameAs<1,2>]>,
|
||||
+ []>;
|
||||
+
|
||||
+def PPCextract_spe : SDNode<"PPCISD::EXTRACT_SPE",
|
||||
+ SDTypeProfile<1, 2,
|
||||
+ [SDTCisInt<0>, SDTCisFP<1>, SDTCisPtrTy<2>]>,
|
||||
+ []>;
|
||||
+
|
||||
// These are target-independent nodes, but have target-specific formats.
|
||||
def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
|
||||
[SDNPHasChain, SDNPOutGlue]>;
|
||||
--- llvm-toolchain-snapshot-9~svn351420.orig/lib/Target/PowerPC/PPCInstrSPE.td
|
||||
+++ llvm-toolchain-snapshot-9~svn351420/lib/Target/PowerPC/PPCInstrSPE.td
|
||||
@@ -512,7 +512,7 @@ def EVLWWSPLATX : EVXForm_1<792, (out
|
||||
|
||||
def EVMERGEHI : EVXForm_1<556, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
|
||||
"evmergehi $RT, $RA, $RB", IIC_VecGeneral, []>;
|
||||
-def EVMERGELO : EVXForm_1<557, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
|
||||
+def EVMERGELO : EVXForm_1<557, (outs sperc:$RT), (ins gprc:$RA, gprc:$RB),
|
||||
"evmergelo $RT, $RA, $RB", IIC_VecGeneral, []>;
|
||||
def EVMERGEHILO : EVXForm_1<558, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
|
||||
"evmergehilo $RT, $RA, $RB", IIC_VecGeneral, []>;
|
||||
@@ -887,4 +887,14 @@ def : Pat<(f64 (selectcc i1:$lhs, i1:$rh
|
||||
(SELECT_SPE (CRANDC $lhs, $rhs), $tval, $fval)>;
|
||||
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
|
||||
(SELECT_SPE (CRXOR $lhs, $rhs), $tval, $fval)>;
|
||||
+
|
||||
+
|
||||
+def : Pat<(f64 (PPCbuild_spe64 i32:$rB, i32:$rA)),
|
||||
+ (f64 (COPY_TO_REGCLASS (EVMERGELO $rA, $rB), SPERC))>;
|
||||
+
|
||||
+def : Pat<(i32 (PPCextract_spe f64:$rA, 1)),
|
||||
+ (i32 (EXTRACT_SUBREG (EVMERGEHI $rA, $rA), sub_32))>;
|
||||
+def : Pat<(i32 (PPCextract_spe f64:$rA, 0)),
|
||||
+ (i32 (EXTRACT_SUBREG $rA, sub_32))>;
|
||||
+
|
||||
}
|
||||
--- llvm-toolchain-snapshot-9~svn351420.orig/test/CodeGen/PowerPC/spe.ll
|
||||
+++ llvm-toolchain-snapshot-9~svn351420/test/CodeGen/PowerPC/spe.ll
|
||||
@@ -472,10 +472,8 @@ entry:
|
||||
; CHECK-LABEL: test_dselect
|
||||
; CHECK: andi.
|
||||
; CHECK: bc
|
||||
-; CHECK: evldd
|
||||
-; CHECK: b
|
||||
-; CHECK: evldd
|
||||
-; CHECK: evstdd
|
||||
+; CHECK: evor
|
||||
+; CHECK: evmergehi
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
@@ -519,7 +517,7 @@ entry:
|
||||
%1 = call i32 asm sideeffect "efdctsi $0, $1", "=d,d"(double %0)
|
||||
ret i32 %1
|
||||
; CHECK-LABEL: test_dasmconst
|
||||
-; CHECK: evldd
|
||||
+; CHECK: evmergelo
|
||||
; CHECK: #APP
|
||||
; CHECK: efdctsi
|
||||
; CHECK: #NO_APP
|
||||
@ -1,137 +0,0 @@
|
||||
Description: PowerPC/SPE: Fix register spilling for SPE registers
|
||||
Author: Justin Hibbits <jrh29@alumni.cwru.edu>
|
||||
Origin: https://reviews.llvm.org/D56703
|
||||
Last-Update: 2019-02-14
|
||||
|
||||
--- llvm-toolchain-snapshot-9~svn351420.orig/lib/Target/PowerPC/PPCCallingConv.td
|
||||
+++ llvm-toolchain-snapshot-9~svn351420/lib/Target/PowerPC/PPCCallingConv.td
|
||||
@@ -346,15 +346,22 @@ def CSR_NoRegs : CalleeSavedRegs<(add)>;
|
||||
// and value may be altered by inter-library calls.
|
||||
// Do not include r12 as it is used as a scratch register.
|
||||
// Do not include return registers r3, f1, v2.
|
||||
-def CSR_SVR32_ColdCC : CalleeSavedRegs<(add (sequence "R%u", 4, 10),
|
||||
- (sequence "R%u", 14, 31),
|
||||
- F0, (sequence "F%u", 2, 31),
|
||||
- (sequence "CR%u", 0, 7))>;
|
||||
+def CSR_SVR32_ColdCC_Common : CalleeSavedRegs<(add (sequence "R%u", 4, 10),
|
||||
+ (sequence "R%u", 14, 31),
|
||||
+ (sequence "CR%u", 0, 7))>;
|
||||
+
|
||||
+def CSR_SVR32_ColdCC : CalleeSavedRegs<(add CSR_SVR32_ColdCC_Common,
|
||||
+ F0, (sequence "F%u", 2, 31))>;
|
||||
+
|
||||
|
||||
def CSR_SVR32_ColdCC_Altivec : CalleeSavedRegs<(add CSR_SVR32_ColdCC,
|
||||
(sequence "V%u", 0, 1),
|
||||
(sequence "V%u", 3, 31))>;
|
||||
|
||||
+def CSR_SVR32_ColdCC_SPE : CalleeSavedRegs<(add CSR_SVR32_ColdCC_Common,
|
||||
+ (sequence "S%u", 4, 10),
|
||||
+ (sequence "S%u", 14, 31))>;
|
||||
+
|
||||
def CSR_SVR64_ColdCC : CalleeSavedRegs<(add (sequence "X%u", 4, 10),
|
||||
(sequence "X%u", 14, 31),
|
||||
F0, (sequence "F%u", 2, 31),
|
||||
--- llvm-toolchain-snapshot-9~svn351420.orig/lib/Target/PowerPC/PPCInstrInfo.cpp
|
||||
+++ llvm-toolchain-snapshot-9~svn351420/lib/Target/PowerPC/PPCInstrInfo.cpp
|
||||
@@ -996,6 +996,8 @@ void PPCInstrInfo::copyPhysReg(MachineBa
|
||||
Opc = PPC::QVFMRb;
|
||||
else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
|
||||
Opc = PPC::CROR;
|
||||
+ else if (PPC::SPE4RCRegClass.contains(DestReg, SrcReg))
|
||||
+ Opc = PPC::OR;
|
||||
else if (PPC::SPERCRegClass.contains(DestReg, SrcReg))
|
||||
Opc = PPC::EVOR;
|
||||
else
|
||||
@@ -1026,10 +1028,10 @@ unsigned PPCInstrInfo::getStoreOpcodeFor
|
||||
OpcodeIndex = SOK_Float8Spill;
|
||||
} else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
|
||||
OpcodeIndex = SOK_Float4Spill;
|
||||
- } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
|
||||
- OpcodeIndex = SOK_SPESpill;
|
||||
} else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
|
||||
OpcodeIndex = SOK_SPE4Spill;
|
||||
+ } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
|
||||
+ OpcodeIndex = SOK_SPESpill;
|
||||
} else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
|
||||
OpcodeIndex = SOK_CRSpill;
|
||||
} else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
|
||||
@@ -1066,6 +1068,10 @@ unsigned PPCInstrInfo::getStoreOpcodeFor
|
||||
OpcodeIndex = SOK_Float8Spill;
|
||||
} else if (PPC::F4RCRegClass.contains(Reg)) {
|
||||
OpcodeIndex = SOK_Float4Spill;
|
||||
+ } else if (PPC::SPE4RCRegClass.contains(Reg)) {
|
||||
+ OpcodeIndex = SOK_SPE4Spill;
|
||||
+ } else if (PPC::SPERCRegClass.contains(Reg)) {
|
||||
+ OpcodeIndex = SOK_SPESpill;
|
||||
} else if (PPC::CRRCRegClass.contains(Reg)) {
|
||||
OpcodeIndex = SOK_CRSpill;
|
||||
} else if (PPC::CRBITRCRegClass.contains(Reg)) {
|
||||
@@ -1112,10 +1118,10 @@ PPCInstrInfo::getLoadOpcodeForSpill(unsi
|
||||
OpcodeIndex = SOK_Float8Spill;
|
||||
} else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
|
||||
OpcodeIndex = SOK_Float4Spill;
|
||||
- } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
|
||||
- OpcodeIndex = SOK_SPESpill;
|
||||
} else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
|
||||
OpcodeIndex = SOK_SPE4Spill;
|
||||
+ } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
|
||||
+ OpcodeIndex = SOK_SPESpill;
|
||||
} else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
|
||||
OpcodeIndex = SOK_CRSpill;
|
||||
} else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
|
||||
@@ -1152,6 +1158,10 @@ PPCInstrInfo::getLoadOpcodeForSpill(unsi
|
||||
OpcodeIndex = SOK_Float8Spill;
|
||||
} else if (PPC::F4RCRegClass.contains(Reg)) {
|
||||
OpcodeIndex = SOK_Float4Spill;
|
||||
+ } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
|
||||
+ OpcodeIndex = SOK_SPE4Spill;
|
||||
+ } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
|
||||
+ OpcodeIndex = SOK_SPESpill;
|
||||
} else if (PPC::CRRCRegClass.contains(Reg)) {
|
||||
OpcodeIndex = SOK_CRSpill;
|
||||
} else if (PPC::CRBITRCRegClass.contains(Reg)) {
|
||||
--- llvm-toolchain-snapshot-9~svn351420.orig/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
||||
+++ llvm-toolchain-snapshot-9~svn351420/lib/Target/PowerPC/PPCRegisterInfo.cpp
|
||||
@@ -167,7 +167,9 @@ PPCRegisterInfo::getCalleeSavedRegs(cons
|
||||
: (SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList
|
||||
: CSR_SVR64_ColdCC_SaveList))
|
||||
: (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_SaveList
|
||||
- : CSR_SVR32_ColdCC_SaveList);
|
||||
+ : (Subtarget.hasSPE()
|
||||
+ ? CSR_SVR32_ColdCC_SPE_SaveList
|
||||
+ : CSR_SVR32_ColdCC_SaveList));
|
||||
}
|
||||
|
||||
return TM.isPPC64()
|
||||
@@ -176,7 +178,9 @@ PPCRegisterInfo::getCalleeSavedRegs(cons
|
||||
: CSR_SVR464_Altivec_SaveList)
|
||||
: (SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList))
|
||||
: (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList
|
||||
- : CSR_SVR432_SaveList);
|
||||
+ : (Subtarget.hasSPE()
|
||||
+ ? CSR_SVR432_SPE_SaveList
|
||||
+ : CSR_SVR432_SaveList));
|
||||
}
|
||||
|
||||
const MCPhysReg *
|
||||
@@ -226,13 +230,17 @@ PPCRegisterInfo::getCallPreservedMask(co
|
||||
return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask
|
||||
: CSR_SVR64_ColdCC_RegMask)
|
||||
: (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_RegMask
|
||||
- : CSR_SVR32_ColdCC_RegMask);
|
||||
+ : (Subtarget.hasSPE()
|
||||
+ ? CSR_SVR32_ColdCC_SPE_RegMask
|
||||
+ : CSR_SVR32_ColdCC_RegMask));
|
||||
}
|
||||
|
||||
return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask
|
||||
: CSR_SVR464_RegMask)
|
||||
: (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask
|
||||
- : CSR_SVR432_RegMask);
|
||||
+ : (Subtarget.hasSPE()
|
||||
+ ? CSR_SVR432_SPE_RegMask
|
||||
+ : CSR_SVR432_RegMask));
|
||||
}
|
||||
|
||||
const uint32_t*
|
||||
5
debian/patches/series
vendored
5
debian/patches/series
vendored
@ -99,11 +99,6 @@ remove-apple-clang-manpage.diff
|
||||
# Hurd port
|
||||
hurd/hurd-pathmax.diff
|
||||
|
||||
# powerpcspe
|
||||
#powerpcspe/D49754-powerpcspe-clang.diff
|
||||
#powerpcspe/D54583-powerpcspe-double-parameter.diff
|
||||
#powerpcspe/D56703-powerpcspe-register-spilling.diff
|
||||
|
||||
# kfreebsd
|
||||
# kfreebsd/clang_lib_Basic_Targets.diff
|
||||
# kfreebsd/CMakeLists.txt.diff
|
||||
|
||||
Loading…
Reference in New Issue
Block a user