From b524862176ee1567aadc303419c95ea095aabb0a Mon Sep 17 00:00:00 2001 From: John Paul Adrian Glaubitz Date: Thu, 14 Feb 2019 16:27:04 +0100 Subject: [PATCH] Update D56703-powerpcspe-register-spilling.diff to latest revision --- debian/changelog | 1 + .../D54409-powerpcspe-register-spilling.diff | 92 ------------ .../D56703-powerpcspe-register-spilling.diff | 137 ++++++++++++++++++ debian/patches/series | 2 +- 4 files changed, 139 insertions(+), 93 deletions(-) delete mode 100644 debian/patches/powerpcspe/D54409-powerpcspe-register-spilling.diff create mode 100644 debian/patches/powerpcspe/D56703-powerpcspe-register-spilling.diff diff --git a/debian/changelog b/debian/changelog index 2284eba4..52a06a28 100644 --- a/debian/changelog +++ b/debian/changelog @@ -4,6 +4,7 @@ llvm-toolchain-snapshot (1:9~svn353106-1~exp2) UNRELEASED; urgency=medium * Update patches for powerpcspe: - D49754-powerpcspe-clang.diff - D54583-powerpcspe-double-parameter.diff + - D56703-powerpcspe-register-spilling.diff -- John Paul Adrian Glaubitz Thu, 14 Feb 2019 16:21:28 +0100 diff --git a/debian/patches/powerpcspe/D54409-powerpcspe-register-spilling.diff b/debian/patches/powerpcspe/D54409-powerpcspe-register-spilling.diff deleted file mode 100644 index 86ff379f..00000000 --- a/debian/patches/powerpcspe/D54409-powerpcspe-register-spilling.diff +++ /dev/null @@ -1,92 +0,0 @@ -Description: PowerPC/SPE: Fix register spilling for SPE registers -Author: Justin Hibbits -Origin: https://reviews.llvm.org/D54409 -Last-Update: 2018-12-05 - -Index: llvm-toolchain-snapshot_9~svn351647/lib/Target/PowerPC/PPCRegisterInfo.cpp -=================================================================== ---- llvm-toolchain-snapshot_9~svn351647.orig/lib/Target/PowerPC/PPCRegisterInfo.cpp -+++ llvm-toolchain-snapshot_9~svn351647/lib/Target/PowerPC/PPCRegisterInfo.cpp -@@ -846,6 +846,9 @@ static unsigned offsetMinAlign(const Mac - case PPC::STXSD: - case PPC::STXSSP: - return 4; -+ case PPC::EVLDD: -+ case PPC::EVSTDD: -+ return 8; - case PPC::LXV: - case PPC::STXV: - return 16; -@@ -962,7 +965,10 @@ PPCRegisterInfo::eliminateFrameIndex(Mac - // happen in invalid code. - assert(OpC != PPC::DBG_VALUE && - "This should be handled in a target-independent way"); -- if (!noImmForm && ((isInt<16>(Offset) && -+ bool canBeImmediate = (OpC == PPC::EVSTDD || OpC == PPC::EVLDD) ? -+ isUInt<8>(Offset) : -+ isInt<16>(Offset); -+ if (!noImmForm && ((canBeImmediate && - ((Offset % offsetMinAlign(MI)) == 0)) || - OpC == TargetOpcode::STACKMAP || - OpC == TargetOpcode::PATCHPOINT)) { -Index: llvm-toolchain-snapshot_9~svn351647/test/CodeGen/PowerPC/spe.ll -=================================================================== ---- llvm-toolchain-snapshot_9~svn351647.orig/test/CodeGen/PowerPC/spe.ll -+++ llvm-toolchain-snapshot_9~svn351647/test/CodeGen/PowerPC/spe.ll -@@ -525,18 +525,53 @@ entry: - ; CHECK: #NO_APP - } - --define double @test_spill(double %a) nounwind { -+declare double @test_spill_spe_regs(double, double); -+define dso_local void @test_func2() #0 { - entry: -+ ret void -+} -+ -+@global_var1 = global i32 0, align 4 -+define double @test_spill(double %a, i32 %a1, i64 %a2, i8 * %a3, i32 *%a4, i32* %a5) nounwind { -+entry: -+ %a.addr = alloca double, align 8 -+ %a1.addr = alloca i32, align 4 -+ %a2.addr = alloca i64, align 8 -+ %a3.addr = alloca i8*, align 4 -+ %a4.addr = alloca i32*, align 4 -+ %a5.addr = alloca i32*, align 4 -+ %ptr = alloca i32*, align 4 -+ %v1 = alloca [8 x i32], align 4 -+ %v2 = alloca [7 x i32], align 4 -+ %v3 = alloca [5 x i32], align 4 -+ store i32 %a1, i32* %a1.addr, align 4 -+ store i64 %a2, i64* %a2.addr, align 8 -+ store i8* %a3, i8** %a3.addr, align 4 -+ store i32* %a4, i32** %a4.addr, align 4 -+ store i32* %a5, i32** %a5.addr, align 4 -+ store i32* @global_var1, i32** %ptr, align 4 - %0 = fadd double %a, %a -- call void asm sideeffect "","~{r0},~{r3},~{s4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind -+ call void asm sideeffect "","~{s0},~{s3},~{s4},~{s5},~{s6},~{s7},~{s8},~{s9},~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s31}"() nounwind - %1 = fadd double %0, 3.14159 -+ %2 = load i32*, i32** %ptr, align 4 -+ %3 = bitcast [8 x i32]* %v1 to i8* -+ call void @llvm.memset.p0i8.i32(i8* align 4 %3, i8 0, i32 24, i1 true) -+ %4 = load i32*, i32** %a5.addr, align 4 -+ store i32 0, i32* %4, align 4 -+ call void @test_func2() -+ %5 = bitcast [7 x i32]* %v2 to i8* -+ call void @llvm.memset.p0i8.i32(i8* align 4 %5, i8 0, i32 20, i1 true) - br label %return - - return: - ret double %1 - - ; CHECK-LABEL: test_spill --; CHECK: efdadd -+; CHECK: li [[VREG:[0-9]+]], 256 -+; CHECK: evstddx {{[0-9]+}}, {{[0-9]+}}, [[VREG]] -+; CHECK-NOT: evstdd {{[0-9]+}}, 256({{[0-9]+}} - ; CHECK: evstdd -+; CHECK: efdadd - ; CHECK: evldd - } -+declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i1) #1 diff --git a/debian/patches/powerpcspe/D56703-powerpcspe-register-spilling.diff b/debian/patches/powerpcspe/D56703-powerpcspe-register-spilling.diff new file mode 100644 index 00000000..82183cf5 --- /dev/null +++ b/debian/patches/powerpcspe/D56703-powerpcspe-register-spilling.diff @@ -0,0 +1,137 @@ +Description: PowerPC/SPE: Fix register spilling for SPE registers +Author: Justin Hibbits +Origin: https://reviews.llvm.org/D56703 +Last-Update: 2019-02-14 + +--- llvm-toolchain-snapshot-9~svn351420.orig/lib/Target/PowerPC/PPCCallingConv.td ++++ llvm-toolchain-snapshot-9~svn351420/lib/Target/PowerPC/PPCCallingConv.td +@@ -346,15 +346,22 @@ def CSR_NoRegs : CalleeSavedRegs<(add)>; + // and value may be altered by inter-library calls. + // Do not include r12 as it is used as a scratch register. + // Do not include return registers r3, f1, v2. +-def CSR_SVR32_ColdCC : CalleeSavedRegs<(add (sequence "R%u", 4, 10), +- (sequence "R%u", 14, 31), +- F0, (sequence "F%u", 2, 31), +- (sequence "CR%u", 0, 7))>; ++def CSR_SVR32_ColdCC_Common : CalleeSavedRegs<(add (sequence "R%u", 4, 10), ++ (sequence "R%u", 14, 31), ++ (sequence "CR%u", 0, 7))>; ++ ++def CSR_SVR32_ColdCC : CalleeSavedRegs<(add CSR_SVR32_ColdCC_Common, ++ F0, (sequence "F%u", 2, 31))>; ++ + + def CSR_SVR32_ColdCC_Altivec : CalleeSavedRegs<(add CSR_SVR32_ColdCC, + (sequence "V%u", 0, 1), + (sequence "V%u", 3, 31))>; + ++def CSR_SVR32_ColdCC_SPE : CalleeSavedRegs<(add CSR_SVR32_ColdCC_Common, ++ (sequence "S%u", 4, 10), ++ (sequence "S%u", 14, 31))>; ++ + def CSR_SVR64_ColdCC : CalleeSavedRegs<(add (sequence "X%u", 4, 10), + (sequence "X%u", 14, 31), + F0, (sequence "F%u", 2, 31), +--- llvm-toolchain-snapshot-9~svn351420.orig/lib/Target/PowerPC/PPCInstrInfo.cpp ++++ llvm-toolchain-snapshot-9~svn351420/lib/Target/PowerPC/PPCInstrInfo.cpp +@@ -996,6 +996,8 @@ void PPCInstrInfo::copyPhysReg(MachineBa + Opc = PPC::QVFMRb; + else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) + Opc = PPC::CROR; ++ else if (PPC::SPE4RCRegClass.contains(DestReg, SrcReg)) ++ Opc = PPC::OR; + else if (PPC::SPERCRegClass.contains(DestReg, SrcReg)) + Opc = PPC::EVOR; + else +@@ -1026,10 +1028,10 @@ unsigned PPCInstrInfo::getStoreOpcodeFor + OpcodeIndex = SOK_Float8Spill; + } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { + OpcodeIndex = SOK_Float4Spill; +- } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) { +- OpcodeIndex = SOK_SPESpill; + } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) { + OpcodeIndex = SOK_SPE4Spill; ++ } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) { ++ OpcodeIndex = SOK_SPESpill; + } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { + OpcodeIndex = SOK_CRSpill; + } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { +@@ -1066,6 +1068,10 @@ unsigned PPCInstrInfo::getStoreOpcodeFor + OpcodeIndex = SOK_Float8Spill; + } else if (PPC::F4RCRegClass.contains(Reg)) { + OpcodeIndex = SOK_Float4Spill; ++ } else if (PPC::SPE4RCRegClass.contains(Reg)) { ++ OpcodeIndex = SOK_SPE4Spill; ++ } else if (PPC::SPERCRegClass.contains(Reg)) { ++ OpcodeIndex = SOK_SPESpill; + } else if (PPC::CRRCRegClass.contains(Reg)) { + OpcodeIndex = SOK_CRSpill; + } else if (PPC::CRBITRCRegClass.contains(Reg)) { +@@ -1112,10 +1118,10 @@ PPCInstrInfo::getLoadOpcodeForSpill(unsi + OpcodeIndex = SOK_Float8Spill; + } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { + OpcodeIndex = SOK_Float4Spill; +- } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) { +- OpcodeIndex = SOK_SPESpill; + } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) { + OpcodeIndex = SOK_SPE4Spill; ++ } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) { ++ OpcodeIndex = SOK_SPESpill; + } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { + OpcodeIndex = SOK_CRSpill; + } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { +@@ -1152,6 +1158,10 @@ PPCInstrInfo::getLoadOpcodeForSpill(unsi + OpcodeIndex = SOK_Float8Spill; + } else if (PPC::F4RCRegClass.contains(Reg)) { + OpcodeIndex = SOK_Float4Spill; ++ } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) { ++ OpcodeIndex = SOK_SPE4Spill; ++ } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) { ++ OpcodeIndex = SOK_SPESpill; + } else if (PPC::CRRCRegClass.contains(Reg)) { + OpcodeIndex = SOK_CRSpill; + } else if (PPC::CRBITRCRegClass.contains(Reg)) { +--- llvm-toolchain-snapshot-9~svn351420.orig/lib/Target/PowerPC/PPCRegisterInfo.cpp ++++ llvm-toolchain-snapshot-9~svn351420/lib/Target/PowerPC/PPCRegisterInfo.cpp +@@ -167,7 +167,9 @@ PPCRegisterInfo::getCalleeSavedRegs(cons + : (SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList + : CSR_SVR64_ColdCC_SaveList)) + : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_SaveList +- : CSR_SVR32_ColdCC_SaveList); ++ : (Subtarget.hasSPE() ++ ? CSR_SVR32_ColdCC_SPE_SaveList ++ : CSR_SVR32_ColdCC_SaveList)); + } + + return TM.isPPC64() +@@ -176,7 +178,9 @@ PPCRegisterInfo::getCalleeSavedRegs(cons + : CSR_SVR464_Altivec_SaveList) + : (SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList)) + : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList +- : CSR_SVR432_SaveList); ++ : (Subtarget.hasSPE() ++ ? CSR_SVR432_SPE_SaveList ++ : CSR_SVR432_SaveList)); + } + + const MCPhysReg * +@@ -226,13 +230,17 @@ PPCRegisterInfo::getCallPreservedMask(co + return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask + : CSR_SVR64_ColdCC_RegMask) + : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_RegMask +- : CSR_SVR32_ColdCC_RegMask); ++ : (Subtarget.hasSPE() ++ ? CSR_SVR32_ColdCC_SPE_RegMask ++ : CSR_SVR32_ColdCC_RegMask)); + } + + return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask + : CSR_SVR464_RegMask) + : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask +- : CSR_SVR432_RegMask); ++ : (Subtarget.hasSPE() ++ ? CSR_SVR432_SPE_RegMask ++ : CSR_SVR432_RegMask)); + } + + const uint32_t* diff --git a/debian/patches/series b/debian/patches/series index 6894b525..a992c529 100644 --- a/debian/patches/series +++ b/debian/patches/series @@ -108,8 +108,8 @@ hurd/impl-path-hurd.diff # powerpcspe powerpcspe/D49754-powerpcspe-clang.diff -powerpcspe/D54409-powerpcspe-register-spilling.diff powerpcspe/D54583-powerpcspe-double-parameter.diff +powerpcspe/D56703-powerpcspe-register-spilling.diff # kfreebsd kfreebsd/clang_lib_Basic_Targets.diff