Merge branch '9-riscv64' into '9'

llvm-toolchain-9: add support for riscv64

See merge request pkg-llvm-team/llvm-toolchain!35

debian/changelog

@@ -7,6 +7,14 @@ llvm-toolchain-9 (1:9~+rc1-1~exp2) experimental; urgency=medium
   * Move lit-cpuid from llvm-tools to lldb (wrong package)
   * Ship clangd-9 as a new package (Closes: #932432)
 
+  [ Aurelien Jarno ]
+  * Add support for riscv64:
+    - Always link with -latomic on riscv64.
+    - patches/clang-riscv64-multiarch.diff: add multiarch paths for riscv64.
+    - patches/clang-riscv64-rv64gc.diff: default to lp64d ABI and rv64gc ISA.
+    - patches/libcxx/libcxx-riscv64-cycletimer.diff: backport riscv64
+      cycletimer support from upstream.
+
  -- Sylvestre Ledru <sylvestre@debian.org>  Sat, 03 Aug 2019 11:41:07 +0200
 
 llvm-toolchain-9 (1:9~+rc1-1~exp1) experimental; urgency=medium

debian/patches/clang-riscv64-multiarch.diff

@@ -0,0 +1,34 @@
+diff --git a/clang/lib/Driver/ToolChains/Linux.cpp b/clang/lib/Driver/ToolChains/Linux.cpp
+index d900508ad93..f516d172b37 100644
+--- a/clang/lib/Driver/ToolChains/Linux.cpp
++++ b/clang/lib/Driver/ToolChains/Linux.cpp
+@@ -150,6 +150,10 @@ static std::string getMultiarchTriple(const Driver &D,
+     if (D.getVFS().exists(SysRoot + "/lib/powerpc64le-linux-gnu"))
+       return "powerpc64le-linux-gnu";
+     break;
++  case llvm::Triple::riscv64:
++    if (D.getVFS().exists(SysRoot + "/lib/riscv64-linux-gnu"))
++      return "riscv64-linux-gnu";
++    break;
+   case llvm::Triple::sparc:
+     if (D.getVFS().exists(SysRoot + "/lib/sparc-linux-gnu"))
+       return "sparc-linux-gnu";
+@@ -749,6 +753,8 @@ void Linux::AddClangSystemIncludeArgs(const ArgList &DriverArgs,
+       "/usr/include/powerpc64-linux-gnu"};
+   const StringRef PPC64LEMultiarchIncludeDirs[] = {
+       "/usr/include/powerpc64le-linux-gnu"};
++  const StringRef RISCV64MultiarchIncludeDirs[] = {
++      "/usr/include/riscv64-linux-gnu"};
+   const StringRef SparcMultiarchIncludeDirs[] = {
+       "/usr/include/sparc-linux-gnu"};
+   const StringRef Sparc64MultiarchIncludeDirs[] = {
+@@ -824,6 +830,9 @@ void Linux::AddClangSystemIncludeArgs(const ArgList &DriverArgs,
+   case llvm::Triple::ppc64le:
+     MultiarchIncludeDirs = PPC64LEMultiarchIncludeDirs;
+     break;
++  case llvm::Triple::riscv64:
++    MultiarchIncludeDirs = RISCV64MultiarchIncludeDirs;
++    break;
+   case llvm::Triple::sparc:
+     MultiarchIncludeDirs = SparcMultiarchIncludeDirs;
+     break;

debian/patches/clang-riscv64-rv64gc.diff

@@ -0,0 +1,38 @@
+diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+index b6768de4d29..9671ea270ef 100644
+--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
++++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+@@ -350,6 +350,13 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const ArgList &Args,
+ 
+     // Handle all other types of extensions.
+     getExtensionFeatures(D, Args, Features, MArch, OtherExts);
++  } else {
++    // Default to imafdc aka gc
++    Features.push_back("+m");
++    Features.push_back("+a");
++    Features.push_back("+f");
++    Features.push_back("+d");
++    Features.push_back("+c");
+   }
+ 
+   // -mrelax is default, unless -mno-relax is specified.
+@@ -375,5 +382,5 @@ StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {
+   if (Arg *A = Args.getLastArg(options::OPT_mabi_EQ))
+     return A->getValue();
+ 
+-  return Triple.getArch() == llvm::Triple::riscv32 ? "ilp32" : "lp64";
++  return Triple.getArch() == llvm::Triple::riscv32 ? "ilp32" : "lp64d";
+ }
+diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
+index 60062d5c327..bb4536cafb0 100644
+--- a/clang/lib/Driver/ToolChains/Clang.cpp
++++ b/clang/lib/Driver/ToolChains/Clang.cpp
+@@ -1850,7 +1850,7 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args,
+   else if (Triple.getArch() == llvm::Triple::riscv32)
+     ABIName = "ilp32";
+   else if (Triple.getArch() == llvm::Triple::riscv64)
+-    ABIName = "lp64";
++    ABIName = "lp64d";
+   else
+     llvm_unreachable("Unexpected triple!");
+ 

debian/patches/libcxx/libcxx-riscv64-cycletimer.diff

@@ -0,0 +1,81 @@
+commit 09e6304440c08fe72b6ac05f922ab9d8b7f1e387
+Author: Roger Ferrer Ibanez <rofirrim@gmail.com>
+Date:   Wed Jul 24 05:33:46 2019 +0000
+
+    [RISCV] Implement benchmark::cycleclock::Now
+    
+    This is a cherrypick of D64237 onto llvm/utils/benchmark and
+    libcxx/utils/google-benchmark.
+    
+    Differential Revision: https://reviews.llvm.org/D65142
+    
+    llvm-svn: 366868
+
+--- a/libcxx/utils/google-benchmark/README.LLVM
++++ b/libcxx/utils/google-benchmark/README.LLVM
+@@ -4,3 +4,9 @@ LLVM notes
+ This directory contains the Google Benchmark source code with some unnecessary
+ files removed. Note that this directory is under a different license than
+ libc++.
++
++Changes:
++* https://github.com/google/benchmark/commit/4abdfbb802d1b514703223f5f852ce4a507d32d2
++  is applied on top of
++  https://github.com/google/benchmark/commit/4528c76b718acc9b57956f63069c699ae21edcab
++  to add RISC-V timer support.
+--- a/libcxx/utils/google-benchmark/src/cycleclock.h
++++ b/libcxx/utils/google-benchmark/src/cycleclock.h
+@@ -164,6 +164,21 @@ inline BENCHMARK_ALWAYS_INLINE int64_t Now() {
+   uint64_t tsc;
+   asm("stck %0" : "=Q"(tsc) : : "cc");
+   return tsc;
++#elif defined(__riscv) // RISC-V
++  // Use RDCYCLE (and RDCYCLEH on riscv32)
++#if __riscv_xlen == 32
++  uint64_t cycles_low, cycles_hi0, cycles_hi1;
++  asm("rdcycleh %0" : "=r"(cycles_hi0));
++  asm("rdcycle %0" : "=r"(cycles_lo));
++  asm("rdcycleh %0" : "=r"(cycles_hi1));
++  // This matches the PowerPC overflow detection, above
++  cycles_lo &= -static_cast<int64_t>(cycles_hi0 == cycles_hi1);
++  return (cycles_hi1 << 32) | cycles_lo;
++#else
++  uint64_t cycles;
++  asm("rdcycle %0" : "=r"(cycles));
++  return cycles;
++#endif
+ #else
+ // The soft failover to a generic implementation is automatic only for ARM.
+ // For other platforms the developer is expected to make an attempt to create
+--- a/utils/benchmark/README.LLVM
++++ b/utils/benchmark/README.LLVM
+@@ -23,3 +23,5 @@ Changes:
+   is applied to disable exceptions in Microsoft STL when exceptions are disabled
+ * Disabled CMake get_git_version as it is meaningless for this in-tree build,
+   and hardcoded a null version
++* https://github.com/google/benchmark/commit/4abdfbb802d1b514703223f5f852ce4a507d32d2
++  is applied on top of v1.4.1 to add RISC-V timer support.
+--- a/utils/benchmark/src/cycleclock.h
++++ b/utils/benchmark/src/cycleclock.h
+@@ -164,6 +164,21 @@ inline BENCHMARK_ALWAYS_INLINE int64_t Now() {
+   uint64_t tsc;
+   asm("stck %0" : "=Q" (tsc) : : "cc");
+   return tsc;
++#elif defined(__riscv) // RISC-V
++  // Use RDCYCLE (and RDCYCLEH on riscv32)
++#if __riscv_xlen == 32
++  uint64_t cycles_low, cycles_hi0, cycles_hi1;
++  asm("rdcycleh %0" : "=r"(cycles_hi0));
++  asm("rdcycle %0" : "=r"(cycles_lo));
++  asm("rdcycleh %0" : "=r"(cycles_hi1));
++  // This matches the PowerPC overflow detection, above
++  cycles_lo &= -static_cast<int64_t>(cycles_hi0 == cycles_hi1);
++  return (cycles_hi1 << 32) | cycles_lo;
++#else
++  uint64_t cycles;
++  asm("rdcycle %0" : "=r"(cycles));
++  return cycles;
++#endif
+ #else
+ // The soft failover to a generic implementation is automatic only for ARM.
+ // For other platforms the developer is expected to make an attempt to create

debian/patches/series

@@ -80,6 +80,7 @@ libcxx/libcxx-test-atomics-set-compare-exchange-to-be-expected-fails-on-arm.patc
 libcxx/libcxx-silent-test-libcxx.diff
 libcxx/libcxx-silent-failure-ppc64el.diff
 libcxx/libcxx-silent-failure-arm64.diff
+libcxx/libcxx-riscv64-cycletimer.diff
 
 # Change default optims
 mips-fpxx-enable.diff
@@ -128,3 +129,6 @@ bootstrap-fix-include-next.diff
 # Python 3
 0050-Remove-explicit-python-version-list.patch
 
+# riscv64
+clang-riscv64-multiarch.diff
+clang-riscv64-rv64gc.diff

debian/rules

@@ -53,9 +53,9 @@ ifneq (,$(filter $(DEB_HOST_ARCH),i386 armel mips mipsel powerpc powerpcspe risc
 CMAKE_EXTRA += -DLIBOMP_LIBFLAGS="-latomic" -DCMAKE_SHARED_LINKER_FLAGS="-latomic"
 endif
 
-ifneq (,$(filter $(DEB_HOST_ARCH),armel))
+ifneq (,$(filter $(DEB_HOST_ARCH),armel riscv64))
 # For some reason, in the stage2 build, when clang is used to compile
-# itself. The atomic detection is failing on armel. Forcing the inclusion everywhere.
+# itself. The atomic detection is failing on armel and riscv64. Forcing the inclusion everywhere.
 LDFLAGS_EXTRA += -latomic
 endif