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rebase of the patch + rename

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This commit is contained in:
Sylvestre Ledru 2020-10-31 22:04:22 +01:00
parent 042d6084d5
commit 9c020b749c
2 changed files with 22 additions and 48 deletions
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68
debian/patches/mips-force-nomadd4.patch vendored
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@ -6,11 +6,11 @@ support both, we have to disabled those instructions.
For that, the patch below basically corresponds to the --with-madd4=no
used on the GCC side.
Index: llvm-toolchain-10-10.0.1~+rc4/clang/lib/Basic/Targets/Mips.h
Index: llvm-toolchain-snapshot_12~++20201031095131+aab71d44431/clang/lib/Basic/Targets/Mips.h
===================================================================
--- llvm-toolchain-10-10.0.1~+rc4.orig/clang/lib/Basic/Targets/Mips.h
+++ llvm-toolchain-10-10.0.1~+rc4/clang/lib/Basic/Targets/Mips.h
@@ -332,6 +332,8 @@
--- llvm-toolchain-snapshot_12~++20201031095131+aab71d44431.orig/clang/lib/Basic/Targets/Mips.h
+++ llvm-toolchain-snapshot_12~++20201031095131+aab71d44431/clang/lib/Basic/Targets/Mips.h
@@ -332,6 +332,8 @@ public:
HasMSA = true;
else if (Feature == "+nomadd4")
DisableMadd4 = true;
@ -19,20 +19,20 @@ Index: llvm-toolchain-10-10.0.1~+rc4/clang/lib/Basic/Targets/Mips.h
else if (Feature == "+fp64")
FPMode = FP64;
else if (Feature == "-fp64")
Index: llvm-toolchain-10-10.0.1~+rc4/llvm/lib/Target/Mips/MipsSubtarget.cpp
Index: llvm-toolchain-snapshot_12~++20201031095131+aab71d44431/llvm/lib/Target/Mips/MipsSubtarget.cpp
===================================================================
--- llvm-toolchain-10-10.0.1~+rc4.orig/llvm/lib/Target/Mips/MipsSubtarget.cpp
+++ llvm-toolchain-10-10.0.1~+rc4/llvm/lib/Target/Mips/MipsSubtarget.cpp
@@ -79,7 +79,7 @@
InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), HasDSPR3(false),
AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
- UseTCCInDIV(false), HasSym32(false), HasEVA(false), DisableMadd4(false),
+ UseTCCInDIV(false), HasSym32(false), HasEVA(false), DisableMadd4(true),
HasMT(false), HasCRC(false), HasVirt(false), HasGINV(false),
UseIndirectJumpsHazard(false), StackAlignOverride(StackAlignOverride),
TM(TM), TargetTriple(TT), TSInfo(),
@@ -91,6 +91,9 @@
--- llvm-toolchain-snapshot_12~++20201031095131+aab71d44431.orig/llvm/lib/Target/Mips/MipsSubtarget.cpp
+++ llvm-toolchain-snapshot_12~++20201031095131+aab71d44431/llvm/lib/Target/Mips/MipsSubtarget.cpp
@@ -80,7 +80,7 @@ MipsSubtarget::MipsSubtarget(const Tripl
InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
- HasEVA(false), DisableMadd4(false), HasMT(false), HasCRC(false),
+ HasEVA(false), DisableMadd4(true), HasMT(false), HasCRC(false),
HasVirt(false), HasGINV(false), UseIndirectJumpsHazard(false),
StackAlignOverride(StackAlignOverride), TM(TM), TargetTriple(TT),
TSInfo(), InstrInfo(MipsInstrInfo::create(
@@ -91,6 +91,9 @@ MipsSubtarget::MipsSubtarget(const Tripl
if (MipsArchVersion == MipsDefault)
MipsArchVersion = Mips32;
@ -42,15 +42,15 @@ Index: llvm-toolchain-10-10.0.1~+rc4/llvm/lib/Target/Mips/MipsSubtarget.cpp
// Don't even attempt to generate code for MIPS-I and MIPS-V. They have not
// been tested and currently exist for the integrated assembler only.
if (MipsArchVersion == Mips1)
@@ -238,6 +241,7 @@
@@ -238,6 +241,7 @@ MipsSubtarget &
MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
const TargetMachine &TM) {
std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
StringRef CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
+ SubtargetFeatures Features(FS);
// Parse features string.
ParseSubtargetFeatures(CPUName, FS);
@@ -260,6 +264,13 @@
ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
@@ -260,6 +264,13 @@ MipsSubtarget::initializeSubtargetDepend
report_fatal_error("64-bit code requested on a subtarget that doesn't "
"support it!");
@ -64,29 +64,3 @@ Index: llvm-toolchain-10-10.0.1~+rc4/llvm/lib/Target/Mips/MipsSubtarget.cpp
return *this;
}
Index: llvm-toolchain-10-10.0.1~+rc4/llvm/lib/Target/Mips/Mips.td
===================================================================
--- llvm-toolchain-10-10.0.1~+rc4.orig/llvm/lib/Target/Mips/Mips.td
+++ llvm-toolchain-10-10.0.1~+rc4/llvm/lib/Target/Mips/Mips.td
@@ -205,7 +205,7 @@
"UseTCCInDIV", "false",
"Force the assembler to use trapping">;
-def FeatureMadd4
+def FeatureNoMadd4
: SubtargetFeature<"nomadd4", "DisableMadd4", "true",
"Disable 4-operand madd.fmt and related instructions">;
Index: llvm-toolchain-10-10.0.1~+rc4/llvm/lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- llvm-toolchain-10-10.0.1~+rc4.orig/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ llvm-toolchain-10-10.0.1~+rc4/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -242,7 +242,7 @@
def HasMSA : Predicate<"Subtarget->hasMSA()">,
AssemblerPredicate<"FeatureMSA">;
def HasMadd4 : Predicate<"!Subtarget->disableMadd4()">,
- AssemblerPredicate<"!FeatureMadd4">;
+ AssemblerPredicate<"!FeatureNoMadd4">;
def HasMT : Predicate<"Subtarget->hasMT()">,
AssemblerPredicate<"FeatureMT">;
def UseIndirectJumpsHazard : Predicate<"Subtarget->useIndirectJumpsHazard()">,

2
debian/patches/series vendored
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@ -83,7 +83,7 @@ libcxx/libcxx-silent-failure-arm64.diff
# Change default optims
mips-fpxx-enable.diff
mips-force-nomadd4.diff
mips-force-nomadd4.patch
26-set-correct-float-abi.diff
clang-baseline-fix-i386.patch
disable-sse2-old-x86.diff