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refresh of the patch

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Sylvestre Ledru 2018-08-30 11:26:30 +02:00
parent 848f86d417
commit 7f1481186f
1 changed files with 59 additions and 57 deletions
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116
debian/patches/pr38663-pgo-lto-crash.patch vendored
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@ -1,5 +1,7 @@
--- llvm-toolchain-6.0-6.0.1~+rc1.orig/lib/CodeGen/PeepholeOptimizer.cpp 2018/03/31 11:38:16 331838
+++ llvm-toolchain-6.0-6.0.1~+rc1/lib/CodeGen/PeepholeOptimizer.cpp 2018/05/20 16:03:21 333926
Index: llvm-toolchain-6.0-6.0.1/lib/CodeGen/PeepholeOptimizer.cpp
===================================================================
--- llvm-toolchain-6.0-6.0.1.orig/lib/CodeGen/PeepholeOptimizer.cpp
+++ llvm-toolchain-6.0-6.0.1/lib/CodeGen/PeepholeOptimizer.cpp
@@ -98,6 +98,8 @@
#include <utility>
@ -9,7 +11,7 @@
#define DEBUG_TYPE "peephole-opt"
@@ -110,6 +112,9 @@
@@ -110,6 +112,9 @@ static cl::opt<bool>
DisablePeephole("disable-peephole", cl::Hidden, cl::init(false),
cl::desc("Disable the peephole optimizer"));
@ -19,7 +21,7 @@
static cl::opt<bool>
DisableAdvCopyOpt("disable-adv-copy-opt", cl::Hidden, cl::init(false),
cl::desc("Disable advanced copy optimization"));
@@ -132,11 +137,11 @@
@@ -132,11 +137,11 @@ static cl::opt<unsigned> MaxRecurrenceCh
"of commuting operands"));
@ -36,7 +38,7 @@
STATISTIC(NumUncoalescableCopies, "Number of uncoalescable copies optimized");
STATISTIC(NumRewrittenCopies, "Number of copies rewritten");
STATISTIC(NumNAPhysCopies, "Number of non-allocatable physical copies removed");
@@ -149,9 +154,9 @@
@@ -149,9 +154,9 @@ namespace {
class PeepholeOptimizer : public MachineFunctionPass {
const TargetInstrInfo *TII;
const TargetRegisterInfo *TRI;
@ -49,7 +51,7 @@
public:
static char ID; // Pass identification
@@ -173,31 +178,28 @@
@@ -173,31 +178,28 @@ namespace {
}
}
@ -93,7 +95,7 @@
DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
/// \brief Finds recurrence cycles, but only ones that formulated around
@@ -212,11 +214,11 @@
@@ -212,11 +214,11 @@ namespace {
/// the set \p CopySrcRegs and \p CopyMIs. If this virtual register was
/// previously seen as a copy, replace the uses of this copy with the
/// previously seen copy's destination register.
@ -107,7 +109,7 @@
bool isNAPhysCopy(unsigned Reg);
/// \brief If copy instruction \p MI is a non-allocatable virtual<->physical
@@ -224,11 +226,10 @@
@@ -224,11 +226,10 @@ namespace {
/// non-allocatable physical register was previously copied to a virtual
/// registered and hasn't been clobbered, the virt->phys copy can be
/// deleted.
@ -121,7 +123,7 @@
SmallSet<unsigned, 16> &FoldAsLoadDefCandidates);
/// \brief Check whether \p MI is understood by the register coalescer
@@ -249,10 +250,13 @@
@@ -249,10 +250,13 @@ namespace {
(MI.isRegSequenceLike() || MI.isInsertSubregLike() ||
MI.isExtractSubregLike()));
}
@ -137,7 +139,7 @@
/// tied use operand, or 2) a def operand and a use operand that is commutable
/// with another use operand which is tied to the def operand. In the latter
/// case, index of the tied use operand and the commutable use operand are
@@ -273,13 +277,13 @@
@@ -273,13 +277,13 @@ namespace {
Optional<IndexPair> CommutePair;
};
@ -155,7 +157,7 @@
/// Instruction using the sources in 'RegSrcs'.
const MachineInstr *Inst = nullptr;
@@ -302,16 +306,20 @@
@@ -302,16 +306,20 @@ namespace {
}
void addSource(unsigned SrcReg, unsigned SrcSubReg) {
@ -178,7 +180,7 @@
unsigned getSrcReg(int Idx) const {
assert(Idx < getNumSources() && "Reg source out of index");
return RegSrcs[Idx].Reg;
@@ -367,59 +375,41 @@
@@ -367,59 +375,41 @@ namespace {
/// The register where the value can be found.
unsigned Reg;
@ -248,7 +250,7 @@
/// If \p Reg is a physical register, a value tracker constructed with
/// this constructor will not find any alternative source.
/// Indeed, when \p Reg is a physical register that constructor does not
@@ -427,46 +417,20 @@
@@ -427,46 +417,20 @@ namespace {
/// Use the next constructor to track a physical register.
ValueTracker(unsigned Reg, unsigned DefSubReg,
const MachineRegisterInfo &MRI,
@ -296,7 +298,7 @@
};
} // end anonymous namespace
@@ -476,11 +440,11 @@
@@ -476,11 +440,11 @@ char PeepholeOptimizer::ID = 0;
char &llvm::PeepholeOptimizerID = PeepholeOptimizer::ID;
INITIALIZE_PASS_BEGIN(PeepholeOptimizer, DEBUG_TYPE,
@ -310,7 +312,7 @@
/// If instruction is a copy-like instruction, i.e. it reads a single register
/// and writes a single register and it does not modify the source, and if the
@@ -491,10 +455,10 @@
@@ -491,10 +455,10 @@ INITIALIZE_PASS_END(PeepholeOptimizer, D
/// the code. Since this code does not currently share EXTRACTs, just ignore all
/// debug uses.
bool PeepholeOptimizer::
@ -323,7 +325,7 @@
return false;
if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||
@@ -535,7 +499,7 @@
@@ -535,7 +499,7 @@ optimizeExtInstr(MachineInstr *MI, Machi
bool ExtendLife = true;
for (MachineOperand &UseMO : MRI->use_nodbg_operands(SrcReg)) {
MachineInstr *UseMI = UseMO.getParent();
@ -332,7 +334,7 @@
continue;
if (UseMI->isPHI()) {
@@ -568,7 +532,7 @@
@@ -568,7 +532,7 @@ optimizeExtInstr(MachineInstr *MI, Machi
continue;
MachineBasicBlock *UseMBB = UseMI->getParent();
@ -341,7 +343,7 @@
// Local uses that come after the extension.
if (!LocalMIs.count(UseMI))
Uses.push_back(&UseMO);
@@ -576,7 +540,7 @@
@@ -576,7 +540,7 @@ optimizeExtInstr(MachineInstr *MI, Machi
// Non-local uses where the result of the extension is used. Always
// replace these unless it's a PHI.
Uses.push_back(&UseMO);
@ -350,7 +352,7 @@
// We may want to extend the live range of the extension result in order
// to replace these uses.
ExtendedUses.push_back(&UseMO);
@@ -640,19 +604,18 @@
@@ -640,19 +604,18 @@ optimizeExtInstr(MachineInstr *MI, Machi
/// against already sets (or could be modified to set) the same flag as the
/// compare, then we can remove the comparison and use the flag from the
/// previous instruction.
@ -373,7 +375,7 @@
++NumCmps;
return true;
}
@@ -661,27 +624,26 @@
@@ -661,27 +624,26 @@ bool PeepholeOptimizer::optimizeCmpInstr
}
/// Optimize a select instruction.
@ -408,7 +410,7 @@
}
/// \brief Try to find the next source that share the same register file
@@ -695,30 +657,29 @@
@@ -695,30 +657,29 @@ bool PeepholeOptimizer::optimizeCondBran
/// share the same register file as \p Reg and \p SubReg. The client should
/// then be capable to rewrite all intermediate PHIs to get the next source.
/// \return False if no alternative sources are available. True otherwise.
@ -447,7 +449,7 @@
// Follow the chain of copies until we find a more suitable source, a phi
// or have to abort.
@@ -747,14 +708,17 @@
@@ -747,14 +708,17 @@ bool PeepholeOptimizer::findNextSource(u
unsigned NumSrcs = Res.getNumSources();
if (NumSrcs > 1) {
PHICount++;
@ -469,7 +471,7 @@
// Do not extend the live-ranges of physical registers as they add
// constraints to the register allocator. Moreover, if we want to extend
// the live-range of a physical register, unlike SSA virtual register,
@@ -764,7 +728,8 @@
@@ -764,7 +728,8 @@ bool PeepholeOptimizer::findNextSource(u
// Keep following the chain if the value isn't any better yet.
const TargetRegisterClass *SrcRC = MRI->getRegClass(CurSrcPair.Reg);
@ -479,7 +481,7 @@
continue;
// We currently cannot deal with subreg operands on PHI instructions
@@ -775,7 +740,7 @@
@@ -775,7 +740,7 @@ bool PeepholeOptimizer::findNextSource(u
// We found a suitable source, and are done with this chain.
break;
}
@ -488,7 +490,7 @@
// If we did not find a more suitable source, there is nothing to optimize.
return CurSrcPair.Reg != Reg;
@@ -786,54 +751,50 @@
@@ -786,54 +751,50 @@ bool PeepholeOptimizer::findNextSource(u
/// successfully traverse a PHI instruction and find suitable sources coming
/// from its edges. By inserting a new PHI, we provide a rewritten PHI def
/// suitable to be used in a new COPY instruction.
@ -563,7 +565,7 @@
/// coalescer friendly. In other words, given a copy-like instruction
/// not all the arguments may be returned at rewritable source, since
/// some arguments are none to be register coalescer friendly.
@@ -848,137 +809,72 @@
@@ -848,137 +809,72 @@ public:
/// the only source this instruction has:
/// (SrcReg, SrcSubReg) = (src, srcSubIdx).
/// This source defines the whole definition, i.e.,
@ -732,7 +734,7 @@
// Find the next non-dead definition and continue from there.
if (CurrentSrcIdx == NumDefs)
return false;
@@ -990,64 +886,27 @@
@@ -990,64 +886,27 @@ public:
}
// What we track are the alternative sources of the definition.
@ -805,7 +807,7 @@
/// Here CopyLike has the following form:
/// dst = INSERT_SUBREG Src1, Src2.src2SubIdx, subIdx.
/// Src1 has the same register class has dst, hence, there is
@@ -1055,29 +914,27 @@
@@ -1055,29 +914,27 @@ public:
/// Src2.src2SubIdx, may not be register coalescer friendly.
/// Therefore, the first call to this method returns:
/// (SrcReg, SrcSubReg) = (Src2, src2SubIdx).
@ -841,7 +843,7 @@
return true;
}
@@ -1092,41 +949,39 @@
@@ -1092,41 +949,39 @@ public:
}
};
@ -892,7 +894,7 @@
return true;
}
@@ -1156,14 +1011,14 @@
@@ -1156,14 +1011,14 @@ public:
}
};
@ -911,7 +913,7 @@
/// Here CopyLike has the following form:
/// dst = REG_SEQUENCE Src1.src1SubIdx, subIdx1, Src2.src2SubIdx, subIdx2.
/// Each call will return a different source, walking all the available
@@ -1171,17 +1026,16 @@
@@ -1171,17 +1026,16 @@ public:
///
/// The first call returns:
/// (SrcReg, SrcSubReg) = (Src1, src1SubIdx).
@ -933,7 +935,7 @@
// We are looking at v0 = REG_SEQUENCE v1, sub1, v2, sub2, etc.
// If this is the first call, move to the first argument.
@@ -1194,17 +1048,17 @@
@@ -1194,17 +1048,17 @@ public:
return false;
}
const MachineOperand &MOInsertedReg = CopyLike.getOperand(CurrentSrcIdx);
@ -955,7 +957,7 @@
// If we have to compose sub-registers, bail.
return MODef.getSubReg() == 0;
}
@@ -1224,16 +1078,14 @@
@@ -1224,16 +1078,14 @@ public:
} // end anonymous namespace
@ -979,7 +981,7 @@
switch (MI.getOpcode()) {
default:
@@ -1247,53 +1099,102 @@
@@ -1247,53 +1099,102 @@ static CopyRewriter *getCopyRewriter(Mac
case TargetOpcode::REG_SEQUENCE:
return new RegSequenceRewriter(MI);
}
@ -1102,7 +1104,7 @@
continue;
// Rewrite source.
@@ -1312,6 +1213,47 @@
@@ -1312,6 +1213,47 @@ bool PeepholeOptimizer::optimizeCoalesca
return Changed;
}
@ -1150,7 +1152,7 @@
/// \brief Optimize copy-like instructions to create
/// register coalescer friendly instruction.
/// The optimization tries to kill-off the \p MI by looking
@@ -1324,48 +1266,40 @@
@@ -1324,48 +1266,40 @@ bool PeepholeOptimizer::optimizeCoalesca
/// been removed from its parent.
/// All COPY instructions created, are inserted in \p LocalMIs.
bool PeepholeOptimizer::optimizeUncoalescableCopy(
@ -1212,7 +1214,7 @@
++NumUncoalescableCopies;
return true;
}
@@ -1374,18 +1308,18 @@
@@ -1374,18 +1308,18 @@ bool PeepholeOptimizer::optimizeUncoales
/// We only fold loads to virtual registers and the virtual register defined
/// has a single use.
bool PeepholeOptimizer::isLoadFoldable(
@ -1236,7 +1238,7 @@
TargetRegisterInfo::isVirtualRegister(Reg) &&
MRI->hasOneNonDBGUse(Reg)) {
FoldAsLoadDefCandidates.insert(Reg);
@@ -1395,16 +1329,16 @@
@@ -1395,16 +1329,16 @@ bool PeepholeOptimizer::isLoadFoldable(
}
bool PeepholeOptimizer::isMoveImmediate(
@ -1258,7 +1260,7 @@
ImmDefRegs.insert(Reg);
return true;
}
@@ -1415,11 +1349,11 @@
@@ -1415,11 +1349,11 @@ bool PeepholeOptimizer::isMoveImmediate(
/// Try folding register operands that are defined by move immediate
/// instructions, i.e. a trivial constant folding optimization, if
/// and only if the def and use are in the same BB.
@ -1274,7 +1276,7 @@
if (!MO.isReg() || MO.isDef())
continue;
// Ignore dead implicit defs.
@@ -1432,7 +1366,7 @@
@@ -1432,7 +1366,7 @@ bool PeepholeOptimizer::foldImmediate(
continue;
DenseMap<unsigned, MachineInstr*>::iterator II = ImmDefMIs.find(Reg);
assert(II != ImmDefMIs.end() && "couldn't find immediate definition");
@ -1283,7 +1285,7 @@
++NumImmFold;
return true;
}
@@ -1454,28 +1388,28 @@
@@ -1454,28 +1388,28 @@ bool PeepholeOptimizer::foldImmediate(
// %2 = COPY %0:sub1
//
// Should replace %2 uses with %1:sub1
@ -1319,7 +1321,7 @@
unsigned PrevSrcSubReg = PrevCopy->getOperand(1).getSubReg();
// Can't replace different subregister extracts.
@@ -1504,19 +1438,19 @@
@@ -1504,19 +1438,19 @@ bool PeepholeOptimizer::isNAPhysCopy(uns
}
bool PeepholeOptimizer::foldRedundantNAPhysCopy(
@ -1344,7 +1346,7 @@
return false;
}
@@ -1528,8 +1462,7 @@
@@ -1528,8 +1462,7 @@ bool PeepholeOptimizer::foldRedundantNAP
if (PrevCopy == NAPhysToVirtMIs.end()) {
// We can't remove the copy: there was an intervening clobber of the
// non-allocatable physical register after the copy to virtual.
@ -1354,7 +1356,7 @@
return false;
}
@@ -1537,7 +1470,7 @@
@@ -1537,7 +1470,7 @@ bool PeepholeOptimizer::foldRedundantNAP
if (PrevDstReg == SrcReg) {
// Remove the virt->phys copy: we saw the virtual register definition, and
// the non-allocatable physical register's state hasn't changed since then.
@ -1363,7 +1365,7 @@
++NumNAPhysCopies;
return true;
}
@@ -1546,7 +1479,7 @@
@@ -1546,7 +1479,7 @@ bool PeepholeOptimizer::foldRedundantNAP
// register get a copy of the non-allocatable physical register, and we only
// track one such copy. Avoid getting confused by this new non-allocatable
// physical register definition, and remove it from the tracked copies.
@ -1372,7 +1374,7 @@
NAPhysToVirtMIs.erase(PrevCopy);
return false;
}
@@ -1611,11 +1544,11 @@
@@ -1611,11 +1544,11 @@ bool PeepholeOptimizer::findTargetRecurr
return false;
}
@ -1389,7 +1391,7 @@
///
/// LoopHeader:
/// %1 = phi(%0, %100)
@@ -1725,27 +1658,25 @@
@@ -1725,27 +1658,25 @@ bool PeepholeOptimizer::runOnMachineFunc
}
if (!MI->isCopy()) {
@ -1425,7 +1427,7 @@
NAPhysToVirtMIs.erase(Def);
}
}
@@ -1761,58 +1692,57 @@
@@ -1761,58 +1692,57 @@ bool PeepholeOptimizer::runOnMachineFunc
// don't know what's correct anymore.
//
// FIXME: handle explicit asm clobbers.
@ -1496,7 +1498,7 @@
!FoldAsLoadDefCandidates.empty()) {
// We visit each operand even after successfully folding a previous
@@ -1861,7 +1791,7 @@
@@ -1861,7 +1791,7 @@ bool PeepholeOptimizer::runOnMachineFunc
// the load candidates. Note: We might be able to fold *into* this
// instruction, so this needs to be after the folding logic.
if (MI->isLoadFoldBarrier()) {
@ -1505,7 +1507,7 @@
FoldAsLoadDefCandidates.clear();
}
}
@@ -1954,14 +1884,14 @@
@@ -1958,14 +1888,14 @@ ValueTrackerResult ValueTracker::getNext
// duplicate the code from the generic TII.
return ValueTrackerResult();
@ -1522,7 +1524,7 @@
if (RegSeqInput.SubIdx == DefSubReg) {
if (RegSeqInput.SubReg)
// Bail if we have to compose sub registers.
@@ -1992,8 +1922,8 @@
@@ -1996,8 +1926,8 @@ ValueTrackerResult ValueTracker::getNext
// duplicate the code from the generic TII.
return ValueTrackerResult();
@ -1533,7 +1535,7 @@
if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg))
return ValueTrackerResult();
@@ -2046,7 +1976,7 @@
@@ -2050,7 +1980,7 @@ ValueTrackerResult ValueTracker::getNext
// duplicate the code from the generic TII.
return ValueTrackerResult();
@ -1542,7 +1544,7 @@
if (!TII->getExtractSubregInputs(*Def, DefIdx, ExtractSubregInputReg))
return ValueTrackerResult();
@@ -2079,7 +2009,7 @@
@@ -2083,7 +2013,7 @@ ValueTrackerResult ValueTracker::getNext
Def->getOperand(3).getImm());
}
@ -1551,16 +1553,16 @@
ValueTrackerResult ValueTracker::getNextSourceFromPHI() {
assert(Def->isPHI() && "Invalid definition");
ValueTrackerResult Res;
@@ -2091,7 +2021,7 @@
@@ -2095,7 +2025,7 @@ ValueTrackerResult ValueTracker::getNext
// Return all register sources for PHI instructions.
for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2) {
- auto &MO = Def->getOperand(i);
+ const MachineOperand &MO = Def->getOperand(i);
assert(MO.isReg() && "Invalid PHI instruction");
Res.addSource(MO.getReg(), MO.getSubReg());
}
@@ -2113,7 +2043,7 @@
// We have no code to deal with undef operands. They shouldn't happen in
// normal programs anyway.
@@ -2121,7 +2051,7 @@ ValueTrackerResult ValueTracker::getNext
return getNextSourceFromBitcast();
// All the remaining cases involve "complex" instructions.
// Bail if we did not ask for the advanced tracking.