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Add patch to optimize double parameter calling setup on powerpcspe
This commit is contained in:
John Paul Adrian Glaubitz
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debian/changelog
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1
debian/changelog
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@ -3,6 +3,7 @@ llvm-toolchain-7 (1:7.0.1~+rc2-9) UNRELEASED; urgency=medium
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[ John Paul Adrian Glaubitz ]
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* Add patch to add powerpcspe support to clang
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* Add patch to fix register spilling on powerpcspe
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* Add patch to optimize double parameter calling setup on powerpcspe
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-- John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> Wed, 05 Dec 2018 09:22:19 +0100
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216
debian/patches/D54584-powerpcspe-double-parameter.diff
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216
debian/patches/D54584-powerpcspe-double-parameter.diff
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@ -0,0 +1,216 @@
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Description: PowerPC: Optimize SPE double parameter calling setup
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Author: Justin Hibbits <jrh29@alumni.cwru.edu>
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Origin: https://reviews.llvm.org/D54583
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Last-Update: 2018-12-04
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--- llvm-toolchain-7-7.0.1~+rc2.orig/lib/Target/PowerPC/PPCISelLowering.cpp
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+++ llvm-toolchain-7-7.0.1~+rc2/lib/Target/PowerPC/PPCISelLowering.cpp
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@@ -389,8 +389,16 @@ PPCTargetLowering::PPCTargetLowering(con
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} else {
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setOperationAction(ISD::BITCAST, MVT::f32, Expand);
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setOperationAction(ISD::BITCAST, MVT::i32, Expand);
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- setOperationAction(ISD::BITCAST, MVT::i64, Expand);
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setOperationAction(ISD::BITCAST, MVT::f64, Expand);
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+ if (Subtarget.hasSPE()) {
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+ setOperationAction(ISD::BITCAST, MVT::i64, Custom);
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+ } else {
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+ setOperationAction(ISD::BITCAST, MVT::i64, Expand);
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+ }
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+ }
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+
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+ if (Subtarget.hasSPE()) {
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+ setOperationAction(ISD::EXTRACT_ELEMENT, MVT::i64, Custom);
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}
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// We cannot sextinreg(i1). Expand to shifts.
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@@ -1355,6 +1363,9 @@ const char *PPCTargetLowering::getTarget
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case PPCISD::QBFLT: return "PPCISD::QBFLT";
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case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
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case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128";
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+ case PPCISD::BUILD_SPE64: return "PPCISD::BUILD_SPE64";
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+ case PPCISD::EXTRACT_SPE_LO: return "PPCISD::EXTRACT_SPE_LO";
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+ case PPCISD::EXTRACT_SPE_HI: return "PPCISD::EXTRACT_SPE_HI";
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}
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return nullptr;
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}
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@@ -7764,6 +7775,15 @@ SDValue PPCTargetLowering::LowerBITCAST(
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SDLoc dl(Op);
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SDValue Op0 = Op->getOperand(0);
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+ if (Subtarget.hasSPE()) {
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+ if (Op.getValueType() == MVT::f64 &&
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+ Op0.getOpcode() == ISD::BUILD_PAIR &&
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+ (Op0.getOperand(1).getValueType() == MVT::i32) &&
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+ (Op0.getOperand(0).getValueType() == MVT::i32))
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+ return DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, Op0.getOperand(0),
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+ Op0.getOperand(1));
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+ }
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+
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if (!EnableQuadPrecision ||
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(Op.getValueType() != MVT::f128 ) ||
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(Op0.getOpcode() != ISD::BUILD_PAIR) ||
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@@ -7775,6 +7795,26 @@ SDValue PPCTargetLowering::LowerBITCAST(
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Op0.getOperand(1));
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}
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+// Lower EXTRACT_ELEMENT (i64 BITCAST f64), 0/1 to evmerge*
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+SDValue PPCTargetLowering::LowerEXTRACT_ELEMENT(SDValue Op, SelectionDAG &DAG) const {
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+
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+ SDLoc dl(Op);
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+ SDValue Op0 = Op->getOperand(0);
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+
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+ if (!Subtarget.hasSPE())
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+ return SDValue();
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+
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+ if (!(Op.getValueType() == MVT::i32 &&
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+ Op0.getOpcode() == ISD::BITCAST))
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+ return SDValue();
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+
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+ assert(Op0.getNumOperands() > 0 && "WTF?");
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+ if (Op->getConstantOperandVal(1) == 0)
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+ return DAG.getNode(PPCISD::EXTRACT_SPE_LO, dl, MVT::i32, Op0.getOperand(0));
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+
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+ return DAG.getNode(PPCISD::EXTRACT_SPE_HI, dl, MVT::i32, Op0.getOperand(0));
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+}
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+
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// If this is a case we can't handle, return null and let the default
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// expansion code take care of it. If we CAN select this case, and if it
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// selects to a single instruction, return Op. Otherwise, if we can codegen
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@@ -9584,6 +9624,8 @@ SDValue PPCTargetLowering::LowerOperatio
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return LowerBSWAP(Op, DAG);
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case ISD::ATOMIC_CMP_SWAP:
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return LowerATOMIC_CMP_SWAP(Op, DAG);
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+ case ISD::EXTRACT_ELEMENT:
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+ return LowerEXTRACT_ELEMENT(Op, DAG);
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}
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}
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@@ -9641,6 +9683,8 @@ void PPCTargetLowering::ReplaceNodeResul
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return;
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Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
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return;
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+ case ISD::BITCAST:
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+ return;
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}
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}
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--- llvm-toolchain-7-7.0.1~+rc2.orig/lib/Target/PowerPC/PPCISelLowering.h
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+++ llvm-toolchain-7-7.0.1~+rc2/lib/Target/PowerPC/PPCISelLowering.h
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@@ -192,6 +192,15 @@ namespace llvm {
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/// Direct move of 2 consective GPR to a VSX register.
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BUILD_FP128,
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+ /// Merge 2 GPRs to a single SPE register
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+ BUILD_SPE64,
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+
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+ /// Extract high SPE register component
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+ EXTRACT_SPE_HI,
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+
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+ /// Extract low SPE register component
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+ EXTRACT_SPE_LO,
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+
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/// Extract a subvector from signed integer vector and convert to FP.
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/// It is primarily used to convert a (widened) illegal integer vector
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/// type to a legal floating point vector type.
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@@ -1079,6 +1088,7 @@ namespace llvm {
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SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
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+ SDValue LowerEXTRACT_ELEMENT(SDValue Op, SelectionDAG &DAG) const;
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SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const;
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--- llvm-toolchain-7-7.0.1~+rc2.orig/lib/Target/PowerPC/PPCInstrInfo.td
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+++ llvm-toolchain-7-7.0.1~+rc2/lib/Target/PowerPC/PPCInstrInfo.td
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@@ -225,6 +225,22 @@ def PPCbuild_fp128: SDNode<"PPCISD::BUIL
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SDTCisSameAs<1,2>]>,
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[]>;
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+def PPCbuild_spe64: SDNode<"PPCISD::BUILD_SPE64",
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+ SDTypeProfile<1, 2,
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+ [SDTCisFP<0>, SDTCisSameSizeAs<1,2>,
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+ SDTCisSameAs<1,2>]>,
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+ []>;
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+
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+def PPCextract_spe_hi : SDNode<"PPCISD::EXTRACT_SPE_HI",
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+ SDTypeProfile<1, 1,
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+ [SDTCisInt<0>, SDTCisFP<1>]>,
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+ []>;
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+
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+def PPCextract_spe_lo : SDNode<"PPCISD::EXTRACT_SPE_LO",
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+ SDTypeProfile<1, 1,
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+ [SDTCisInt<0>, SDTCisFP<1>]>,
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+ []>;
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+
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// These are target-independent nodes, but have target-specific formats.
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
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[SDNPHasChain, SDNPOutGlue]>;
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--- llvm-toolchain-7-7.0.1~+rc2.orig/lib/Target/PowerPC/PPCInstrSPE.td
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+++ llvm-toolchain-7-7.0.1~+rc2/lib/Target/PowerPC/PPCInstrSPE.td
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@@ -512,7 +512,7 @@ def EVLWWSPLATX : EVXForm_1<792, (out
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def EVMERGEHI : EVXForm_1<556, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
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"evmergehi $RT, $RA, $RB", IIC_VecGeneral, []>;
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-def EVMERGELO : EVXForm_1<557, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
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+def EVMERGELO : EVXForm_1<557, (outs sperc:$RT), (ins gprc:$RA, gprc:$RB),
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"evmergelo $RT, $RA, $RB", IIC_VecGeneral, []>;
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def EVMERGEHILO : EVXForm_1<558, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
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"evmergehilo $RT, $RA, $RB", IIC_VecGeneral, []>;
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@@ -889,4 +889,15 @@ def : Pat<(f64 (selectcc i1:$lhs, i1:$rh
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(SELECT_SPE (CRANDC $lhs, $rhs), $tval, $fval)>;
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def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
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(SELECT_SPE (CRXOR $lhs, $rhs), $tval, $fval)>;
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+
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+
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+def : Pat<(f64 (PPCbuild_spe64 i32:$rB, i32:$rA)),
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+ (f64 (COPY_TO_REGCLASS (EVMERGELO $rA, $rB), SPERC))>;
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+
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+def : Pat<(i32 (PPCextract_spe_hi f64:$rA)),
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+ (i32 (EXTRACT_SUBREG (EVMERGEHI $rA, $rA), sub_32))>;
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+
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+def : Pat<(i32 (PPCextract_spe_lo f64:$rA)),
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+ (i32 (EXTRACT_SUBREG $rA, sub_32))>;
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+
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}
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--- llvm-toolchain-7-7.0.1~+rc2.orig/test/CodeGen/PowerPC/spe.ll
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+++ llvm-toolchain-7-7.0.1~+rc2/test/CodeGen/PowerPC/spe.ll
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@@ -472,10 +472,8 @@ entry:
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; CHECK-LABEL: test_dselect
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; CHECK: andi.
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; CHECK: bc
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-; CHECK: evldd
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-; CHECK: b
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-; CHECK: evldd
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-; CHECK: evstdd
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+; CHECK: evor
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+; CHECK: evmergehi
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; CHECK: blr
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}
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@@ -519,7 +517,7 @@ entry:
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%1 = call i32 asm sideeffect "efdctsi $0, $1", "=d,d"(double %0)
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ret i32 %1
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; CHECK-LABEL: test_dasmconst
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-; CHECK: evldd
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+; CHECK: evmergelo
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; CHECK: #APP
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; CHECK: efdctsi
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; CHECK: #NO_APP
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@@ -541,7 +539,7 @@ entry:
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%a4.addr = alloca i32*, align 4
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%a5.addr = alloca i32*, align 4
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%ptr = alloca i32*, align 4
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- %v1 = alloca [8 x i32], align 4
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+ %v1 = alloca [9 x i32], align 4
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%v2 = alloca [7 x i32], align 4
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%v3 = alloca [5 x i32], align 4
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store i32 %a1, i32* %a1.addr, align 4
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@@ -554,7 +552,7 @@ entry:
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call void asm sideeffect "","~{s0},~{s3},~{s4},~{s5},~{s6},~{s7},~{s8},~{s9},~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s31}"() nounwind
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%1 = fadd double %0, 3.14159
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%2 = load i32*, i32** %ptr, align 4
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- %3 = bitcast [8 x i32]* %v1 to i8*
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+ %3 = bitcast [9 x i32]* %v1 to i8*
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call void @llvm.memset.p0i8.i32(i8* align 4 %3, i8 0, i32 24, i1 true)
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%4 = load i32*, i32** %a5.addr, align 4
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store i32 0, i32* %4, align 4
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1
debian/patches/series
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1
debian/patches/series
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@ -107,3 +107,4 @@ strip-ignore-deterministic-archives.diff
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# powerpcspe
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D49754-powerpcspe-clang.diff
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D54409-powerpcspe-register-spilling.diff
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D54584-powerpcspe-double-parameter.diff
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