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rebase of the patches
This commit is contained in:
Sylvestre Ledru
parent
ad29ec1841
commit
61d26018dd
@ -3,11 +3,11 @@ Author: Justin Hibbits <jrh29@alumni.cwru.edu>
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Origin: https://reviews.llvm.org/D54583
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Last-Update: 2018-12-04
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Index: llvm-toolchain-snapshot_8~svn349138/lib/Target/PowerPC/PPCISelLowering.cpp
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Index: llvm-toolchain-snapshot_8~svn350421/lib/Target/PowerPC/PPCISelLowering.cpp
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===================================================================
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--- llvm-toolchain-snapshot_8~svn349138.orig/lib/Target/PowerPC/PPCISelLowering.cpp
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+++ llvm-toolchain-snapshot_8~svn349138/lib/Target/PowerPC/PPCISelLowering.cpp
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@@ -391,8 +391,16 @@ PPCTargetLowering::PPCTargetLowering(con
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--- llvm-toolchain-snapshot_8~svn350421.orig/lib/Target/PowerPC/PPCISelLowering.cpp
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+++ llvm-toolchain-snapshot_8~svn350421/lib/Target/PowerPC/PPCISelLowering.cpp
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@@ -385,8 +385,16 @@ PPCTargetLowering::PPCTargetLowering(con
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} else {
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setOperationAction(ISD::BITCAST, MVT::f32, Expand);
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setOperationAction(ISD::BITCAST, MVT::i32, Expand);
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@ -25,7 +25,7 @@ Index: llvm-toolchain-snapshot_8~svn349138/lib/Target/PowerPC/PPCISelLowering.cp
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}
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// We cannot sextinreg(i1). Expand to shifts.
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@@ -1351,6 +1359,9 @@ const char *PPCTargetLowering::getTarget
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@@ -1366,6 +1374,9 @@ const char *PPCTargetLowering::getTarget
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case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
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case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128";
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case PPCISD::EXTSWSLI: return "PPCISD::EXTSWSLI";
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@ -35,7 +35,7 @@ Index: llvm-toolchain-snapshot_8~svn349138/lib/Target/PowerPC/PPCISelLowering.cp
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}
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return nullptr;
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}
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@@ -7859,6 +7870,15 @@ SDValue PPCTargetLowering::LowerBITCAST(
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@@ -7886,6 +7897,15 @@ SDValue PPCTargetLowering::LowerBITCAST(
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SDLoc dl(Op);
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SDValue Op0 = Op->getOperand(0);
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@ -51,7 +51,7 @@ Index: llvm-toolchain-snapshot_8~svn349138/lib/Target/PowerPC/PPCISelLowering.cp
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if (!EnableQuadPrecision ||
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(Op.getValueType() != MVT::f128 ) ||
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(Op0.getOpcode() != ISD::BUILD_PAIR) ||
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@@ -7870,6 +7890,26 @@ SDValue PPCTargetLowering::LowerBITCAST(
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@@ -7897,6 +7917,26 @@ SDValue PPCTargetLowering::LowerBITCAST(
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Op0.getOperand(1));
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}
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@ -78,7 +78,7 @@ Index: llvm-toolchain-snapshot_8~svn349138/lib/Target/PowerPC/PPCISelLowering.cp
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// If this is a case we can't handle, return null and let the default
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// expansion code take care of it. If we CAN select this case, and if it
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// selects to a single instruction, return Op. Otherwise, if we can codegen
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@@ -9643,6 +9683,8 @@ SDValue PPCTargetLowering::LowerOperatio
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@@ -9680,6 +9720,8 @@ SDValue PPCTargetLowering::LowerOperatio
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return LowerBSWAP(Op, DAG);
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case ISD::ATOMIC_CMP_SWAP:
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return LowerATOMIC_CMP_SWAP(Op, DAG);
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@ -87,10 +87,10 @@ Index: llvm-toolchain-snapshot_8~svn349138/lib/Target/PowerPC/PPCISelLowering.cp
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}
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}
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Index: llvm-toolchain-snapshot_8~svn349138/lib/Target/PowerPC/PPCISelLowering.h
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Index: llvm-toolchain-snapshot_8~svn350421/lib/Target/PowerPC/PPCISelLowering.h
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===================================================================
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--- llvm-toolchain-snapshot_8~svn349138.orig/lib/Target/PowerPC/PPCISelLowering.h
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+++ llvm-toolchain-snapshot_8~svn349138/lib/Target/PowerPC/PPCISelLowering.h
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--- llvm-toolchain-snapshot_8~svn350421.orig/lib/Target/PowerPC/PPCISelLowering.h
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+++ llvm-toolchain-snapshot_8~svn350421/lib/Target/PowerPC/PPCISelLowering.h
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@@ -196,6 +196,15 @@ namespace llvm {
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/// Direct move of 2 consective GPR to a VSX register.
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BUILD_FP128,
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@ -107,7 +107,7 @@ Index: llvm-toolchain-snapshot_8~svn349138/lib/Target/PowerPC/PPCISelLowering.h
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/// Extract a subvector from signed integer vector and convert to FP.
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/// It is primarily used to convert a (widened) illegal integer vector
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/// type to a legal floating point vector type.
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@@ -1089,6 +1098,7 @@ namespace llvm {
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@@ -1110,6 +1119,7 @@ namespace llvm {
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SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
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@ -115,10 +115,10 @@ Index: llvm-toolchain-snapshot_8~svn349138/lib/Target/PowerPC/PPCISelLowering.h
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SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const;
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Index: llvm-toolchain-snapshot_8~svn349138/lib/Target/PowerPC/PPCInstrInfo.td
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Index: llvm-toolchain-snapshot_8~svn350421/lib/Target/PowerPC/PPCInstrInfo.td
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===================================================================
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--- llvm-toolchain-snapshot_8~svn349138.orig/lib/Target/PowerPC/PPCInstrInfo.td
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+++ llvm-toolchain-snapshot_8~svn349138/lib/Target/PowerPC/PPCInstrInfo.td
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--- llvm-toolchain-snapshot_8~svn350421.orig/lib/Target/PowerPC/PPCInstrInfo.td
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+++ llvm-toolchain-snapshot_8~svn350421/lib/Target/PowerPC/PPCInstrInfo.td
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@@ -231,6 +231,22 @@ def PPCbuild_fp128: SDNode<"PPCISD::BUIL
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SDTCisSameAs<1,2>]>,
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[]>;
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@ -142,10 +142,10 @@ Index: llvm-toolchain-snapshot_8~svn349138/lib/Target/PowerPC/PPCInstrInfo.td
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// These are target-independent nodes, but have target-specific formats.
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
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[SDNPHasChain, SDNPOutGlue]>;
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Index: llvm-toolchain-snapshot_8~svn349138/lib/Target/PowerPC/PPCInstrSPE.td
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Index: llvm-toolchain-snapshot_8~svn350421/lib/Target/PowerPC/PPCInstrSPE.td
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===================================================================
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--- llvm-toolchain-snapshot_8~svn349138.orig/lib/Target/PowerPC/PPCInstrSPE.td
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+++ llvm-toolchain-snapshot_8~svn349138/lib/Target/PowerPC/PPCInstrSPE.td
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--- llvm-toolchain-snapshot_8~svn350421.orig/lib/Target/PowerPC/PPCInstrSPE.td
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+++ llvm-toolchain-snapshot_8~svn350421/lib/Target/PowerPC/PPCInstrSPE.td
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@@ -512,7 +512,7 @@ def EVLWWSPLATX : EVXForm_1<792, (out
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def EVMERGEHI : EVXForm_1<556, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
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@ -171,10 +171,10 @@ Index: llvm-toolchain-snapshot_8~svn349138/lib/Target/PowerPC/PPCInstrSPE.td
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+ (i32 (EXTRACT_SUBREG $rA, sub_32))>;
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+
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}
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Index: llvm-toolchain-snapshot_8~svn349138/test/CodeGen/PowerPC/spe.ll
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Index: llvm-toolchain-snapshot_8~svn350421/test/CodeGen/PowerPC/spe.ll
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===================================================================
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--- llvm-toolchain-snapshot_8~svn349138.orig/test/CodeGen/PowerPC/spe.ll
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+++ llvm-toolchain-snapshot_8~svn349138/test/CodeGen/PowerPC/spe.ll
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--- llvm-toolchain-snapshot_8~svn350421.orig/test/CodeGen/PowerPC/spe.ll
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+++ llvm-toolchain-snapshot_8~svn350421/test/CodeGen/PowerPC/spe.ll
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@@ -472,10 +472,8 @@ entry:
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; CHECK-LABEL: test_dselect
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; CHECK: andi.
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16
debian/patches/lldb-soname.diff
vendored
16
debian/patches/lldb-soname.diff
vendored
@ -2,13 +2,13 @@
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lldb/source/API/CMakeLists.txt | 14 +++++++-------
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1 file changed, 7 insertions(+), 7 deletions(-)
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Index: llvm-toolchain-snapshot_8~svn349138/lldb/source/API/CMakeLists.txt
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Index: llvm-toolchain-snapshot_8~svn350421/lldb/source/API/CMakeLists.txt
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===================================================================
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--- llvm-toolchain-snapshot_8~svn349138.orig/lldb/source/API/CMakeLists.txt
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+++ llvm-toolchain-snapshot_8~svn349138/lldb/source/API/CMakeLists.txt
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@@ -4,7 +4,12 @@ endif()
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get_property(LLDB_ALL_PLUGINS GLOBAL PROPERTY LLDB_PLUGINS)
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--- llvm-toolchain-snapshot_8~svn350421.orig/lldb/source/API/CMakeLists.txt
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+++ llvm-toolchain-snapshot_8~svn350421/lldb/source/API/CMakeLists.txt
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@@ -9,7 +9,12 @@ if(NOT LLDB_DISABLE_PYTHON)
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set(lldb_python_wrapper ${lldb_scripts_dir}/LLDBWrapPython.cpp)
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endif()
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-add_lldb_library(liblldb SHARED
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+set(output_name lldb)
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@ -20,7 +20,7 @@ Index: llvm-toolchain-snapshot_8~svn349138/lldb/source/API/CMakeLists.txt
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SBAddress.cpp
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SBAttachInfo.cpp
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SBBlock.cpp
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@@ -113,7 +118,7 @@ endif ()
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@@ -120,7 +125,7 @@ endif()
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set_target_properties(liblldb
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PROPERTIES
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@ -29,7 +29,7 @@ Index: llvm-toolchain-snapshot_8~svn349138/lldb/source/API/CMakeLists.txt
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)
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if (NOT CMAKE_SYSTEM_NAME MATCHES "Windows")
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@@ -137,11 +142,6 @@ if ( CMAKE_SYSTEM_NAME MATCHES "Windows"
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@@ -144,11 +149,6 @@ if ( CMAKE_SYSTEM_NAME MATCHES "Windows"
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if (MSVC AND NOT LLDB_DISABLE_PYTHON)
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target_link_libraries(liblldb PRIVATE ${PYTHON_LIBRARY})
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endif()
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