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fix the patch
This commit is contained in:
Sylvestre Ledru
parent
b07636d37b
commit
515e8931a5
142
debian/patches/amdgpu-regression.diff
vendored
142
debian/patches/amdgpu-regression.diff
vendored
@ -1,104 +1,104 @@
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Index: llvm-toolchain-3.9-3.9.1/lib/Target/AMDGPU/SIInstructions.td
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===================================================================
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--- llvm-toolchain-3.9-3.9.1.orig/lib/Target/AMDGPU/SIInstructions.td
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+++ llvm-toolchain-3.9-3.9.1/lib/Target/AMDGPU/SIInstructions.td
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@@ -2029,6 +2029,7 @@ def SI_RETURN : PseudoInstSI <
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let hasSideEffects = 1;
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let SALU = 1;
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let hasNoSchedulingInfo = 1;
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+ let DisableWQM = 1;
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}
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let Uses = [EXEC], Defs = [EXEC, VCC, M0],
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Index: llvm-toolchain-3.9-3.9.1/lib/Target/AMDGPU/SIWholeQuadMode.cpp
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Index: llvm-toolchain-3.9-3.9.1/lib/Target/AMDGPU/SIWholeQuadMode.cpp
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===================================================================
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===================================================================
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--- llvm-toolchain-3.9-3.9.1.orig/lib/Target/AMDGPU/SIWholeQuadMode.cpp
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--- llvm-toolchain-3.9-3.9.1.orig/lib/Target/AMDGPU/SIWholeQuadMode.cpp
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+++ llvm-toolchain-3.9-3.9.1/lib/Target/AMDGPU/SIWholeQuadMode.cpp
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+++ llvm-toolchain-3.9-3.9.1/lib/Target/AMDGPU/SIWholeQuadMode.cpp
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@@ -219,13 +219,6 @@ char SIWholeQuadMode::scanInstructions(M
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@@ -219,6 +219,13 @@ char SIWholeQuadMode::scanInstructions(M
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markInstruction(MI, Flags, Worklist);
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markInstruction(MI, Flags, Worklist);
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GlobalFlags |= Flags;
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GlobalFlags |= Flags;
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}
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}
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-
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+
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- if (WQMOutputs && MBB.succ_empty()) {
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+ if (WQMOutputs && MBB.succ_empty()) {
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- // This is a prolog shader. Make sure we go back to exact mode at the end.
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+ // This is a prolog shader. Make sure we go back to exact mode at the end.
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- Blocks[&MBB].OutNeeds = StateExact;
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+ Blocks[&MBB].OutNeeds = StateExact;
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- Worklist.push_back(&MBB);
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+ Worklist.push_back(&MBB);
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- GlobalFlags |= StateExact;
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+ GlobalFlags |= StateExact;
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- }
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+ }
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}
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}
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return GlobalFlags;
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return GlobalFlags;
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Index: llvm-toolchain-3.9-3.9.1/lib/Target/AMDGPU/SIInstructions.td
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===================================================================
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--- llvm-toolchain-3.9-3.9.1.orig/lib/Target/AMDGPU/SIInstructions.td
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+++ llvm-toolchain-3.9-3.9.1/lib/Target/AMDGPU/SIInstructions.td
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@@ -2029,7 +2029,6 @@ def SI_RETURN : PseudoInstSI <
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let hasSideEffects = 1;
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let SALU = 1;
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let hasNoSchedulingInfo = 1;
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- let DisableWQM = 1;
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}
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let Uses = [EXEC], Defs = [EXEC, VCC, M0],
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Index: llvm-toolchain-3.9-3.9.1/test/CodeGen/AMDGPU/wqm.ll
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Index: llvm-toolchain-3.9-3.9.1/test/CodeGen/AMDGPU/wqm.ll
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===================================================================
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===================================================================
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--- llvm-toolchain-3.9-3.9.1.orig/test/CodeGen/AMDGPU/wqm.ll
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--- llvm-toolchain-3.9-3.9.1.orig/test/CodeGen/AMDGPU/wqm.ll
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+++ llvm-toolchain-3.9-3.9.1/test/CodeGen/AMDGPU/wqm.ll
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+++ llvm-toolchain-3.9-3.9.1/test/CodeGen/AMDGPU/wqm.ll
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@@ -17,17 +17,18 @@ main_body:
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@@ -17,18 +17,17 @@ main_body:
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;CHECK-LABEL: {{^}}test2:
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;CHECK-LABEL: {{^}}test2:
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;CHECK-NEXT: ; %main_body
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;CHECK-NEXT: ; %main_body
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;CHECK-NEXT: s_wqm_b64 exec, exec
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;CHECK-NEXT: s_wqm_b64 exec, exec
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-;CHECK: image_sample
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+;CHECK: image_sample
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;CHECK-NOT: exec
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;CHECK-NOT: exec
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-;CHECK: _load_dword v0,
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-define amdgpu_ps void @test2(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <4 x i32> %c) {
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-define amdgpu_ps float @test2(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <4 x i32> %c) {
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+;CHECK: _load_dword v0,
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+define amdgpu_ps void @test2(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <4 x i32> %c) {
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+define amdgpu_ps float @test2(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <4 x i32> %c) {
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main_body:
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main_body:
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%c.1 = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%c.1 = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%c.2 = bitcast <4 x float> %c.1 to <4 x i32>
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%c.2 = bitcast <4 x float> %c.1 to <4 x i32>
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%c.3 = extractelement <4 x i32> %c.2, i32 0
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%c.3 = extractelement <4 x i32> %c.2, i32 0
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%gep = getelementptr float, float addrspace(1)* %ptr, i32 %c.3
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%gep = getelementptr float, float addrspace(1)* %ptr, i32 %c.3
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%data = load float, float addrspace(1)* %gep
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%data = load float, float addrspace(1)* %gep
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- ret float %data
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-
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+
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- call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %data, float undef, float undef, float undef)
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+ call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %data, float undef, float undef, float undef)
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-
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+
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- ret void
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+ ret void
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+ ret float %data
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}
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}
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; ... but disabled for stores (and, in this simple case, not re-enabled).
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; ... but disabled for stores (and, in this simple case, not re-enabled).
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@@ -414,6 +415,46 @@ entry:
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@@ -415,46 +414,6 @@ entry:
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ret void
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ret void
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}
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}
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+; Must return to exact at the end of a non-void returning shader,
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-; Must return to exact at the end of a non-void returning shader,
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+; otherwise the EXEC mask exported by the epilog will be wrong. This is true
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-; otherwise the EXEC mask exported by the epilog will be wrong. This is true
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+; even if the shader has no kills, because a kill could have happened in a
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-; even if the shader has no kills, because a kill could have happened in a
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+; previous shader fragment.
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-; previous shader fragment.
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+;
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-;
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+; CHECK-LABEL: {{^}}test_nonvoid_return:
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-; CHECK-LABEL: {{^}}test_nonvoid_return:
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+; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec
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-; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec
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+; CHECK: s_wqm_b64 exec, exec
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-; CHECK: s_wqm_b64 exec, exec
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+;
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-;
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+; CHECK: s_and_b64 exec, exec, [[LIVE]]
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-; CHECK: s_and_b64 exec, exec, [[LIVE]]
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+; CHECK-NOT: exec
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-; CHECK-NOT: exec
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+define amdgpu_ps <4 x float> @test_nonvoid_return() nounwind {
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-define amdgpu_ps <4 x float> @test_nonvoid_return() nounwind {
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+ %tex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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- %tex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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+ %tex.i = bitcast <4 x float> %tex to <4 x i32>
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- %tex.i = bitcast <4 x float> %tex to <4 x i32>
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+ %dtex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %tex.i, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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- %dtex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %tex.i, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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+ ret <4 x float> %dtex
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- ret <4 x float> %dtex
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+}
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-}
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+
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-
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+; CHECK-LABEL: {{^}}test_nonvoid_return_unreachable:
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-; CHECK-LABEL: {{^}}test_nonvoid_return_unreachable:
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+; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec
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-; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec
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+; CHECK: s_wqm_b64 exec, exec
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-; CHECK: s_wqm_b64 exec, exec
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+;
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-;
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+; CHECK: s_and_b64 exec, exec, [[LIVE]]
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-; CHECK: s_and_b64 exec, exec, [[LIVE]]
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+; CHECK-NOT: exec
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-; CHECK-NOT: exec
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+define amdgpu_ps <4 x float> @test_nonvoid_return_unreachable(i32 inreg %c) nounwind {
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-define amdgpu_ps <4 x float> @test_nonvoid_return_unreachable(i32 inreg %c) nounwind {
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+entry:
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-entry:
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+ %tex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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- %tex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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+ %tex.i = bitcast <4 x float> %tex to <4 x i32>
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- %tex.i = bitcast <4 x float> %tex to <4 x i32>
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+ %dtex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %tex.i, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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- %dtex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %tex.i, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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+
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-
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+ %cc = icmp sgt i32 %c, 0
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- %cc = icmp sgt i32 %c, 0
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+ br i1 %cc, label %if, label %else
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- br i1 %cc, label %if, label %else
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+
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-
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+if:
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-if:
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+ store volatile <4 x float> %dtex, <4 x float>* undef
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- store volatile <4 x float> %dtex, <4 x float>* undef
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+ unreachable
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- unreachable
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+
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-
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+else:
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-else:
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+ ret <4 x float> %dtex
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- ret <4 x float> %dtex
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+}
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-}
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declare void @llvm.amdgcn.image.store.v4i32(<4 x float>, <4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #1
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declare void @llvm.amdgcn.image.store.v4i32(<4 x float>, <4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #1
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declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) #1
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declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) #1
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