Merge remote-tracking branch 'origin/7' into snapshot

2025-08-03 06:57:55 +00:00 · 2018-09-11 11:44:16 +02:00 · 2018-09-11 11:44:16 +02:00 · 4731d96b7e
commit 4731d96b7e
parent df88ae4433 9c65b1e79c
8 changed files with 1914 additions and 0 deletions
--- a/.gitattributes
+++ b/.gitattributes
@ -0,0 +1,6 @@
+debian/changelog merge=dpkg-mergechangelogs
+
+#  ~/.gitconfig should have
+# [merge "dpkg-mergechangelogs"]
+# name = debian/changelog merge driver
+# driver = dpkg-mergechangelogs -m %O %A %B %A 
--- a/debian/changelog
+++ b/debian/changelog
@ -71,6 +71,17 @@ llvm-toolchain-snapshot (1:8~svn340819-1) unstable; urgency=medium

 -- Sylvestre Ledru <sylvestre@debian.org>  Tue, 28 Aug 2018 16:28:24 +0200

+llvm-toolchain-7 (1:7~+rc3-1) unstable; urgency=medium
+
+  [ John Paul Adrian Glaubitz ]
+  * Disable OpenMP on unsupported architectures powerpc,
+    powerpcspe, riscv64 and sparc64 (Closes: #907912)
+
+  [ Sylvestre Ledru ]
+  * New snapshot release
+
+ -- Sylvestre Ledru <sylvestre@debian.org>  Mon, 10 Sep 2018 17:01:25 +0200
+
 llvm-toolchain-7 (1:7~+rc1-1~exp2) experimental; urgency=medium

  * Disable force-gcc-header-obj.diff as it is introducing
--- a/debian/patches/D51108-rust-powerpc.diff
+++ b/debian/patches/D51108-rust-powerpc.diff
--- a/debian/patches/D51335-alignment-issue.diff
+++ b/debian/patches/D51335-alignment-issue.diff
@ -0,0 +1,107 @@
+Index: llvm-toolchain-6.0-6.0.1/lib/Transforms/Scalar/SROA.cpp
+===================================================================
+--- llvm-toolchain-6.0-6.0.1.orig/lib/Transforms/Scalar/SROA.cpp
+++ llvm-toolchain-6.0-6.0.1/lib/Transforms/Scalar/SROA.cpp
+@@ -2987,6 +2987,42 @@ private:
+     return true;
+   }
+ 
+  void fixLoadStoreAlign(Instruction &Root) {
+    // This algorithm implements the same visitor loop as
+    // hasUnsafePHIOrSelectUse, and fixes the alignment of each load
+    // or store found.
+    SmallPtrSet<Instruction *, 4> Visited;
+    SmallVector<Instruction *, 4> Uses;
+    Visited.insert(&Root);
+    Uses.push_back(&Root);
+    do {
+      Instruction *I = Uses.pop_back_val();
+
+      if (LoadInst *LI = dyn_cast<LoadInst>(I)) {
+        unsigned LoadAlign = LI->getAlignment();
+        if (!LoadAlign)
+          LoadAlign = DL.getABITypeAlignment(LI->getType());
+        LI->setAlignment(std::min(LoadAlign, getSliceAlign()));
+        continue;
+      }
+      if (StoreInst *SI = dyn_cast<StoreInst>(I)) {
+        unsigned StoreAlign = SI->getAlignment();
+        if (!StoreAlign) {
+          Value *Op = SI->getOperand(0);
+          StoreAlign = DL.getABITypeAlignment(Op->getType());
+        }
+        SI->setAlignment(std::min(StoreAlign, getSliceAlign()));
+        continue;
+      }
+
+      assert(isa<BitCastInst>(I) || isa<PHINode>(I) ||
+             isa<SelectInst>(I) || isa<GetElementPtrInst>(I));
+      for (User *U : I->users())
+        if (Visited.insert(cast<Instruction>(U)).second)
+          Uses.push_back(cast<Instruction>(U));
+    } while (!Uses.empty());
+  }
+
+   bool visitPHINode(PHINode &PN) {
+     DEBUG(dbgs() << "    original: " << PN << "\n");
+     assert(BeginOffset >= NewAllocaBeginOffset && "PHIs are unsplittable");
+@@ -3010,6 +3046,9 @@ private:
+     DEBUG(dbgs() << "          to: " << PN << "\n");
+     deleteIfTriviallyDead(OldPtr);
+ 
+    // Fix the alignment of any loads or stores using this PHI node.
+    fixLoadStoreAlign(PN);
+
+     // PHIs can't be promoted on their own, but often can be speculated. We
+     // check the speculation outside of the rewriter so that we see the
+     // fully-rewritten alloca.
+@@ -3034,6 +3073,9 @@ private:
+     DEBUG(dbgs() << "          to: " << SI << "\n");
+     deleteIfTriviallyDead(OldPtr);
+ 
+    // Fix the alignment of any loads or stores using this select.
+    fixLoadStoreAlign(SI);
+
+     // Selects can't be promoted on their own, but often can be speculated. We
+     // check the speculation outside of the rewriter so that we see the
+     // fully-rewritten alloca.
+Index: llvm-toolchain-6.0-6.0.1/test/Transforms/SROA/phi-and-select.ll
+===================================================================
+--- llvm-toolchain-6.0-6.0.1.orig/test/Transforms/SROA/phi-and-select.ll
+++ llvm-toolchain-6.0-6.0.1/test/Transforms/SROA/phi-and-select.ll
+@@ -600,3 +600,35 @@ if.then5:
+   store %struct.S undef, %struct.S* %f1, align 4
+   ret void
+ }
+
+define i32 @phi_align(i32* %z) {
+; CHECK-LABEL: @phi_align(
+entry:
+  %a = alloca [8 x i8], align 8
+; CHECK: alloca [7 x i8]
+
+  %a0x = getelementptr [8 x i8], [8 x i8]* %a, i64 0, i32 1
+  %a0 = bitcast i8* %a0x to i32*
+  %a1x = getelementptr [8 x i8], [8 x i8]* %a, i64 0, i32 4
+  %a1 = bitcast i8* %a1x to i32*
+; CHECK: store i32 0, {{.*}}, align 1
+  store i32 0, i32* %a0, align 1
+; CHECK: store i32 1, {{.*}}, align 1
+  store i32 1, i32* %a1, align 4
+; CHECK: load {{.*}}, align 1
+  %v0 = load i32, i32* %a0, align 1
+; CHECK: load {{.*}}, align 1
+  %v1 = load i32, i32* %a1, align 4
+  %cond = icmp sle i32 %v0, %v1
+  br i1 %cond, label %then, label %exit
+
+then:
+  br label %exit
+
+exit:
+; CHECK: %phi = phi i32* [ {{.*}}, %then ], [ %z, %entry ]
+; CHECK-NEXT: %result = load i32, i32* %phi, align 1
+  %phi = phi i32* [ %a1, %then ], [ %z, %entry ]
+  %result = load i32, i32* %phi, align 4
+  ret i32 %result
+}
--- a/debian/patches/D51639-optim-issue.diff
+++ b/debian/patches/D51639-optim-issue.diff
@ -0,0 +1,46 @@
+Index: llvm-toolchain-6.0-6.0.1/lib/Transforms/Vectorize/LoopVectorize.cpp
+===================================================================
+--- llvm-toolchain-6.0-6.0.1.orig/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ llvm-toolchain-6.0-6.0.1/lib/Transforms/Vectorize/LoopVectorize.cpp
+@@ -4529,6 +4529,11 @@
+       // isOutOfScope operands cannot be uniform instructions.
+       if (isOutOfScope(OV))
+         continue;
+      // First order recurrence Phi's should typically be considered
+      // non-uniform.
+      auto *OP = dyn_cast<PHINode>(OV);
+      if (OP && Legal->isFirstOrderRecurrence(OP))
+        continue;
+       // If all the users of the operand are uniform, then add the
+       // operand into the uniform worklist.
+       auto *OI = cast<Instruction>(OV);
+Index: llvm-toolchain-6.0-6.0.1/test/Transforms/LoopVectorize/X86/uniform-phi.ll
+===================================================================
+--- llvm-toolchain-6.0-6.0.1.orig/test/Transforms/LoopVectorize/X86/uniform-phi.ll
+++ llvm-toolchain-6.0-6.0.1/test/Transforms/LoopVectorize/X86/uniform-phi.ll
+@@ -75,3 +75,25 @@
+   ret i64 %retval
+ }
+ 
+; CHECK-LABEL: PR38786
+; Check that first order recurrence phis (%phi32 and %phi64) are not uniform.
+; CHECK-NOT: LV: Found uniform instruction:   %phi
+define void @PR38786(double* %y, double* %x, i64 %n) {
+entry:
+  br label %for.body
+
+for.body:
+  %phi32 = phi i32 [ 0, %entry ], [ %i32next, %for.body ]
+  %phi64 = phi i64 [ 0, %entry ], [ %i64next, %for.body ]
+  %i32next = add i32 %phi32, 1
+  %i64next = zext i32 %i32next to i64
+  %xip = getelementptr inbounds double, double* %x, i64 %i64next
+  %yip = getelementptr inbounds double, double* %y, i64 %phi64
+  %xi = load double, double* %xip, align 8
+  store double %xi, double* %yip, align 8
+  %cmp = icmp slt i64 %i64next, %n
+  br i1 %cmp, label %for.body, label %for.end
+
+for.end:
+  ret void
+}
--- a/debian/patches/pr38663-pgo-lto-crash.patch
+++ b/debian/patches/pr38663-pgo-lto-crash.patch
--- a/debian/patches/rL338481-cherry-pick-really-subtle-miscompile.diff
+++ b/debian/patches/rL338481-cherry-pick-really-subtle-miscompile.diff
@ -0,0 +1,153 @@
+Index: llvm-toolchain-6.0-6.0.1/test/CodeGen/X86/flags-copy-lowering.mir
+===================================================================
+--- llvm-toolchain-6.0-6.0.1.orig/test/CodeGen/X86/flags-copy-lowering.mir
+++ llvm-toolchain-6.0-6.0.1/test/CodeGen/X86/flags-copy-lowering.mir
+@@ -72,6 +72,18 @@
+     call void @foo()
+     ret void
+   }
+
+  define i32 @test_existing_setcc(i64 %a, i64 %b) {
+  entry:
+    call void @foo()
+    ret i32 0
+  }
+
+  define i32 @test_existing_setcc_memory(i64 %a, i64 %b) {
+  entry:
+    call void @foo()
+    ret i32 0
+  }
+ ...
+ ---
+ name:            test_branch
+@@ -553,3 +565,110 @@ body:             |
+     RET 0
+ 
+ ...
+---
+name:            test_existing_setcc
+# CHECK-LABEL: name: test_existing_setcc
+liveins:
+  - { reg: '$rdi', virtual-reg: '%0' }
+  - { reg: '$rsi', virtual-reg: '%1' }
+body:             |
+  bb.0:
+    successors: %bb.1, %bb.2, %bb.3
+    liveins: $rdi, $rsi
+
+    %0:gr64 = COPY $rdi
+    %1:gr64 = COPY $rsi
+    CMP64rr %0, %1, implicit-def $eflags
+    %2:gr8 = SETAr implicit $eflags
+    %3:gr8 = SETAEr implicit $eflags
+    %4:gr64 = COPY $eflags
+  ; CHECK:      CMP64rr %0, %1, implicit-def $eflags
+  ; CHECK-NEXT: %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags
+  ; CHECK-NEXT: %[[AE_REG:[^:]*]]:gr8 = SETAEr implicit $eflags
+  ; CHECK-NOT:  COPY{{( killed)?}} $eflags
+
+    ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+    CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
+    ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+
+    $eflags = COPY %4
+    JA_1 %bb.1, implicit $eflags
+    JB_1 %bb.2, implicit $eflags
+    JMP_1 %bb.3
+  ; CHECK-NOT: $eflags =
+  ;
+  ; CHECK:        TEST8rr %[[A_REG]], %[[A_REG]], implicit-def $eflags
+  ; CHECK-NEXT:   JNE_1 %bb.1, implicit killed $eflags
+  ; CHECK-SAME: {{$[[:space:]]}}
+  ; CHECK-NEXT: bb.4:
+  ; CHECK-NEXT:   successors: {{.*$}}
+  ; CHECK-SAME: {{$[[:space:]]}}
+  ; CHECK-NEXT:   TEST8rr %[[AE_REG]], %[[AE_REG]], implicit-def $eflags
+  ; CHECK-NEXT:   JE_1 %bb.2, implicit killed $eflags
+  ; CHECK-NEXT:   JMP_1 %bb.3
+
+  bb.1:
+    %5:gr32 = MOV32ri64 42
+    $eax = COPY %5
+    RET 0, $eax
+
+  bb.2:
+    %6:gr32 = MOV32ri64 43
+    $eax = COPY %6
+    RET 0, $eax
+
+  bb.3:
+    %7:gr32 = MOV32r0 implicit-def dead $eflags
+    $eax = COPY %7
+    RET 0, $eax
+
+...
+---
+name:            test_existing_setcc_memory
+# CHECK-LABEL: name: test_existing_setcc_memory
+liveins:
+  - { reg: '$rdi', virtual-reg: '%0' }
+  - { reg: '$rsi', virtual-reg: '%1' }
+body:             |
+  bb.0:
+    successors: %bb.1, %bb.2
+    liveins: $rdi, $rsi
+
+    %0:gr64 = COPY $rdi
+    %1:gr64 = COPY $rsi
+    CMP64rr %0, %1, implicit-def $eflags
+    SETEm %0, 1, $noreg, -16, $noreg, implicit $eflags
+    %2:gr64 = COPY $eflags
+  ; CHECK:      CMP64rr %0, %1, implicit-def $eflags
+  ; We cannot reuse this SETE because it stores the flag directly to memory,
+  ; so we have two SETEs here. FIXME: It'd be great if something could fold
+  ; these automatically. If not, maybe we want to unfold SETcc instructions
+  ; writing to memory so we can reuse them.
+  ; CHECK-NEXT: SETEm {{.*}} implicit $eflags
+  ; CHECK-NEXT: %[[E_REG:[^:]*]]:gr8 = SETEr implicit $eflags
+  ; CHECK-NOT:  COPY{{( killed)?}} $eflags
+
+    ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+    CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
+    ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+
+    $eflags = COPY %2
+    JE_1 %bb.1, implicit $eflags
+    JMP_1 %bb.2
+  ; CHECK-NOT: $eflags =
+  ;
+  ; CHECK:        TEST8rr %[[E_REG]], %[[E_REG]], implicit-def $eflags
+  ; CHECK-NEXT:   JNE_1 %bb.1, implicit killed $eflags
+  ; CHECK-NEXT:   JMP_1 %bb.2
+
+  bb.1:
+    %3:gr32 = MOV32ri64 42
+    $eax = COPY %3
+    RET 0, $eax
+
+  bb.2:
+    %4:gr32 = MOV32ri64 43
+    $eax = COPY %4
+    RET 0, $eax
+
+...
+Index: llvm-toolchain-6.0-6.0.1/lib/Target/X86/X86FlagsCopyLowering.cpp
+===================================================================
+--- llvm-toolchain-6.0-6.0.1.orig/lib/Target/X86/X86FlagsCopyLowering.cpp
+++ llvm-toolchain-6.0-6.0.1/lib/Target/X86/X86FlagsCopyLowering.cpp
+@@ -608,9 +608,12 @@ X86FlagsCopyLoweringPass::collectCondsIn
+   for (MachineInstr &MI : llvm::reverse(
+            llvm::make_range(MBB.instr_begin(), CopyDefI.getIterator()))) {
+     X86::CondCode Cond = X86::getCondFromSETOpc(MI.getOpcode());
+-    if (Cond != X86::COND_INVALID && MI.getOperand(0).isReg() &&
+-        TRI->isVirtualRegister(MI.getOperand(0).getReg()))
+    if (Cond != X86::COND_INVALID && !MI.mayStore() && MI.getOperand(0).isReg() &&
+        TRI->isVirtualRegister(MI.getOperand(0).getReg())) {
+      assert(MI.getOperand(0).isDef() &&
+             "A non-storing SETcc should always define a register!");
+       CondRegs[Cond] = MI.getOperand(0).getReg();
+    }
+ 
+     // Stop scanning when we see the first definition of the EFLAGS as prior to
+     // this we would potentially capture the wrong flag state.
--- a/debian/qualify-clang.sh
+++ b/debian/qualify-clang.sh
@ -332,6 +332,24 @@ echo "Test: CMake find LLVM and Clang in explicit prefix path"
 (cd cmaketest/explicit && CC=clang-$VERSION CXX=clang++-$VERSION CMAKE_PREFIX_PATH=/usr/lib/llvm-$VERSION cmake ..)
 rm -rf cmaketest

+# Test case for bug #900440
+rm -rf cmaketest && mkdir cmaketest
+cat > cmaketest/CMakeLists.txt <<EOF
+cmake_minimum_required(VERSION 2.8.12)
+project(testllvm)
+
+find_package(LLVM CONFIG REQUIRED)
+find_package(Clang CONFIG REQUIRED)
+
+if(NOT LLVM_VERSION STREQUAL Clang_VERSION)
+    #message(FATAL_ERROR "LLVM ${LLVM_VERSION} not matching to Clang ${Clang_VERSION}")
+endif()
+EOF
+mkdir cmaketest/foo/
+(cd cmaketest/foo && cmake ..)
+rm -rf cmaketest
+
+
 CLANG=clang-$VERSION
 #command -v "$CLANG" 1>/dev/null 2>/dev/null || { printf "Usage:\n%s CLANGEXE [ARGS]\n" "$0" 1>&2; exit 1; }
 #shift